UDP Offload not receiving
Hi I am using the UDP Offload example. the only difference is that instead of the packet checker i have a custom component that just outputs the avalon ST signal for my hardware to use. Here is the...
View ArticleInstalling Quartus 13.0 in Ubuntu 12.04 64 bit
Hi, We are having trouble installing Quartus 13.0 in Ubuntu 12.04 64 bit. Here is the procedure that we followed: 1. Download Quartus 13.0 subscription edition from Altera's website 2. Navigated to...
View ArticleVectored Interrupt Controller causes stuck in alt_tick()
Hi, I am facing issues when using the Vectored Interrupt Controller with the Nios. Sometimes I experience that my Nios seems to crash and when pressing pause during debug I find that the system gets...
View ArticleCyclone V: Communication with EPCQ Device in User Mode after Bootup
For my design, I'm using the Cyclone V (5CEFA7F23). I'm looking to boot the "factory image" from an EPCQ flash device using Active Serial x4, and then from the factory image (when in user mode),...
View ArticleGet Cyclone Device ID using Serial Configuration Device
I'd like to read the device ID from the FPGA that is being programmed using a serial configuration device. I know how to do it with JTAG but with this being Active Serial I'm stumped. Can it be done...
View Articlecontrol LPT port
Hello In my sdudy final project I use CPLD in order to make some operations. I control the /cpld via the computer parallel port. Because the port is not bidirectional, but requires a time open it in...
View ArticleWhat is the impact of having illegal clock and unconstraint clock in the design
Anyone can tell me what is the impact of having illegal clock and unconstraint clock reported in the timequest? Worst come to worst, what will be the direct impact from the hardware performance?...
View ArticleNIOS II Processing Getting Reset with SDRAM
I have developed a hardware design with Nios II processor using the DE0 board with Quartus v12. I am using a cpu, a sys clk timer, an interval timer, jtag uart, system id, sdram and pios. . When I run...
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Altera JTAG Problem
Hello ~ We are using the 3 stratix4 as 1 chain, but it is separated from JTAG for flash rom. In other words, JTAG signals are shared for 3FPGAs. Program for EPC device is okay, but problem is about...
View Articlekernel panic when reboot linux
Dear all, This is a very strange issue,I run linux on NIOS at CYCLONE 4. After download linux image,system can boot successfully. But when I execute command reboot in UART shell or push reset...
View ArticleHow to read NIOS-II General Purpose Register's
How to read NIOS-II General purpose Register specifically R29 (Exception return Address) & R30 (Breakpoint return Address) NIOS-II Processor Reference Handbook Page 3-11
View ArticleMixed sign math problem
The background: I'm working on QAM modulation from a Cyclone II dev board with a DAC board I made connected to it. Works great as a DDS and everything other than the QAM math. The main QAM calculation...
View Articlewhether or not GXLB0 and GXLB1 can share one refclk in the Cyclone V GX?
In the Cyclone V handbook Pgae 65, "Cyclone V devices have one dedicated reference clock (refclk) pin for each bank of three transceiver channels." I want to know whether or not two bank of six...
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Problems with Cyclone IV and DP83848C
Dear all, I've made my own board of Cyclone IV EP4CGX110CF23C7. And i want to make a ethernet module with DP83848C which is surpported by the TSE core. However, when i have completed my SOPC system and...
View Articleparallel port programming via PC
Hello In my sdudy final project I use CPLD in order to make some operations. I control the cpld via the computer parallel port. Because the port is not bidirectional, but requires a time open it in any...
View Articleprintf thread safe ?
Dear all, I am using printf() in a task to display debug information in a Nios terminal window. However, I was wondering if printf() is thread safe. I am facing some buggy behaviour which I suspect to...
View ArticleQSys doesn't properly create all output files during generation
I'm working with QSys (Quartus II, V13.0) on a NIOS II based design imported from SOPC builder. If I generate the output files for Quartus, not all required files seem to be properly build. (Simulation...
View ArticleArithmetics on Virtual Signals in Modelsim
Hi guys, Can I in some way do arithmetic on signals I'm viewing in ModelSim? F.x. I have two signals signalA(7 downto 0) signalB(7 downto 0) and in ModelSim I want to view a wave form mySignal =...
View ArticlePCI-express LINUX Driver for NIOS2
Hi, I am working on Altera STRATIX-IV . I got success in porting Linux on NIOS2 using uClinux-dist with linux version 2.6 Now i have to add PCI-express root port driver to the kernel. After selecting...
View ArticleCan not modprobe any driver
Hi guys I have strange situation. Some time ago I realized that I can not load any module to Linux (I'm working with MMU). I wrote then simple driver to check: #include <linux/init.h> #include...
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