Changing cyclone II I/O current strength without re-synthesis
Hi, I would like to change several FPGA IO's current strength but without re-synthesis the project. the project is old and already functions "on the field", hence, we prefer to reduce risks as much as...
View Articlesystem console: get_service_paths jtag_debug return null in stratixV
Hi, which mega function I should use to have jtag_debug service ? In Qsys, it has JTAG to Avalon Master Bridge but I don't find the similar one in mega wizard manager. I have my block diagram already...
View ArticleClik here to view.
Can't use 2 pins together on a single IDC connector (Altera DE1 Development Kit)
Hi. I have a problem with using 2 pins together on a single IDC connector. I don't have signal on each of 2 pins of single IDC connector. If I use only 1 pin on a single IDC connector, I can see...
View ArticleCycloneIII Vs CycloneIV :: Urgent Help Required
Hello, I am using below devices for my two seperate projects having same RTL and exactly similar Synthesis/PAR settings. Project 1: set_option -technology CYCLONEIII set_option -part EP3C120 set_option...
View ArticlePCIe hard IP - MSI-X Capabilities are incorrect
Hello, I'm using the PCIe hard IP on a Cyclone IV GX device. I enabled MSI-X and configured MSI-X Capabilities using the Megawizard. The actual contents of the implemented capability registers seem to...
View ArticleTCP/IP Offload Engine Implementations -- What's the big deal?
Hi all, I've recently begun a project where I have to build a TCP/IP offload engine (maintain at least a few dozen TCP sessions; calculate checksums, maintain some state for each, retransmission...
View ArticleClik here to view.
Problem with FFT of 32768 points and more
Hello, I have created a FFT with MegaWizard Plug-in Manager of the 13.0 Quartus version, with the following parameters : Target Device family : Stratix IIITransform Length : 16384, 32768Data Input...
View ArticleDDIO clock timing
Hi, I'm using a Stratix III EP3SL340 C3 (Terasic DE3) and I had a question about DDIO. I have 12 bit data from an ADC (AFE5807) coming in at 80MSPS. I wanted to use DDIO to receive the data. I'll...
View Articlealtera 13.0 uniphy pin assign script fails if...
FWIW, the altera 13.0 ddr2 uniphy pin assign script (against stratix III) appears to fail if "adv_netlist_opt_synth_gate_retime" option is on. The workaround is to turn the...
View ArticleFIFO queue
hey everyone, I was wondering how to write a FIFO queue code using verilog. I am unable to start it even. it will be great if someone can help me in this matter. Cheers Muzammil
View ArticleUSB device developmet using NIOS II and Altera USB Core
OK, so I really want to know this. I can see that USB core exists for the Altera FPGAs, I think that Nios II or a HPS would be needed to be used with this USB controller core. I cannot find any...
View ArticleProfiling tools for uClinux
Hi, I realized that gprof does not work with uClinux, unfortunately. Nevertheless, oprofile is an another solution and I tryed to install it. But, I have problems with system's generation: Code:...
View ArticleWhat is the mean of process corner?
When I do timing simulation or STA, it is relevant to an condition that is "process corner". I am a little confusing about this definition. My understanding is: this is a graph which horizontal and...
View ArticleForwarding circuitry for memory in QuartusII
Hello, I want to add a forwarding circuitry to a memory design to make the data available even before I store it. If anybody knows how to do this kindly let me know. Are there any libraries in Quartus...
View ArticleDDR3 IP simulation error Error: (vsim-10000) Unresolved defparamreference to...
While simulatintg the DDR3 SDRAM Uniphy IP example desing I am getting below given Errors :- Error: (vsim-10000) ./..//submodules/altera_mem_if_hard_memory_controller_top_cyclonev. sv(1621): Unresolved...
View ArticleThe explanation of gray code quadrant technique
Many articles discuss about the benefits of using gray counter to design a FIFO. One of the advantage is we can use the quadrant coding method to determine the FIFO empty and full condition. Yes, i can...
View ArticleCan we specify cut timing path along with the code?
Hello, I have a toggle synchronizer like below and want to exclude the domain crossing register transfer ce_t1 <= ce_toggle from timing analysis. Is there any way to do it automatically, e.g. by a...
View Article[ModelSim simulation problem] $hold??
Hi ~there, I'm using ModelSim to do a simulation about viterbi decode simulation. I use Verilog HDL and FPGA and the device is one of altera cyclone III series . But unfortunately a problem happens,...
View ArticleMulticore Design using Nios II with Accelerator
Hi everyone, I have to design a system with Nios II multicore with an Accelerator or more accelerators for my Project. I am new in Nios II so, it's difficult for me to start with. can anyone please...
View Articleknown issues about the GPRS software or driver
Hi, i'm wondering if someone has a list of problems regarding the GPRS connection on uClinux with Nios2. What i mean is that i'm looking for well known problems on : the ppp module provided by the...
View Article