I have two clock signals: clock_50 (50MHz) and clock (16kHz). Now I want FPGA to do three commands within each clock (16kHz), the commands are done in one clock_50 (50MHz).
I tried but it doesn't work. The idea is the same following lines, but I dont know how to code it
Could you please help me?
I tried but it doesn't work. The idea is the same following lines, but I dont know how to code it
Code:
always @(posedge clock) begin
always @(posedge clock_50) begin
//do a command
//do a command
//do a command
end
end