how to access TSE control port?
Hello all, I've checked all the possible solutions to get TSE working in gigabit mode, like pll rx and all the suggestion by an440 but no way. There's another suggestion by accessing a "control port"...
View Articlelookup table (LUT) in Verilog
I know there are many ways to implement a LUT on FPGA. I am trying to use case statement for this implementation because it is very easy. Basically, what I am trying to get is an one dimentional array....
View ArticleWhat kind of JTAG this board is using?
Hello, I'm following a tutorial PCB board for Cyclone 4. I'm using the design found here provided by one man has done it before: https://bitbucket.org/avakar/omicron...ard?at=default In his board, he...
View ArticleNios II erase sector
I'm working on cyclone III with the EPCS64, in my Nios code C the time delay of erasing for one sector is defined at 3 seconds to be sure of the erasing, I would like to know if there is a way to...
View ArticleCyclone IV: Pll input clk
Hello, I need to know if it is possible to select as pll input a clk signal with a duty cycle different of 50%/50%. Could this imbalance influence the properly generation of pll outputs? Thanks in...
View ArticleDecrease configuration time
Hi all, I have a Cyclone III LS set for Standard AS configuration (MSEL[3:0] = 0010) using an EPCS64 to store the config file. I'd rather not make a PCB change, so the MSEL pins will probably have to...
View ArticleDownloading ELF Process failed Arria V GX Starter Kit
Hi, I am currently receiving errors regarding downloading the ELF process to my Arria V GX starter kit. Basically what I am trying to do is complete the nichestack tutorial (for cyclone III, V and...
View ArticleHelp, error occur during compilation. Can anyone help me please
Help, error occur during compilation. Can anyone help me please Error list “ 175001 could not place fractional PLL 12289 an error occurred while applying the peripheryconstraints. Review the offending...
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Multi IO voltage JTAG
My circuit is composed 4 Stratix4s per chain. And each FPGA has multiple IO voltage. (see attachment picture) Vccio of each FPGA's bank1A is connected to 2.5V. So we connected pull-up to 2.5V. But in...
View ArticleCyclone V SoC Dev Kit, CAN connector pin assignment
Hi, i just recently started to develop a CAN application for the Cyclone V SoC, and now tried to connect to my PC using a CAN adapter. Unfortunately the pin assignment isn't part of the hardware...
View ArticleFPGAs under university program
I would like to inquire into the possibility of obtaining a few FPGAs under the University program. I am an undergraduate student and would like to procure some FPGAs for my student project set to...
View Article3.3V LVCMOS termination absent in Cyclone V??
Hello, I looked at Table 5-29: Selectable I/O Standards for RS OCT Without Calibration and Table 5-30: Selectable I/O Standards for RS OCT With Calibration from Cyclone V Device Handbook, and It seems...
View ArticlePeak CPU load
Hi, MicroC/OS-II has a statistics task which allows you to monitor CPU load with the OSCPUUsage variable. This runs fine but I am interested in measuring peak performance. Does anybody know a method to...
View ArticleNios2: DMA+FIFO
Hi everybody. I'm trying to transmit array from onchip memory through DMA to on chip FIFO and then read data from FIFO to another array. Parameters are as follows: fifo - depth=1024, dual clock mode,...
View ArticleResitor Terminsion for LVDS ARRIA V
Hi all, I'm designing a new board with LVDS connection: On the receiver side, I implemented (on my quartus design) a deserialiser at 85MHz for a 7 serialise factor. I read on the device handbook that I...
View ArticlePipeline latency
Suppose I would like to know how many cycles deep is my kernel pipeline. Is this information readily available from any .log file generated by AOCL? Thank you,
View ArticleCheck two different clocks
I have two clock signals: clock_50 (50MHz) and clock (16kHz). Now I want FPGA to do three commands within each clock (16kHz), the commands are done in one clock_50 (50MHz). I tried but it doesn't work....
View ArticleCyclone III Dev Kit Cooling Requirement
We are planning on using a Cyclone III Dev Kit (DK-DEV-3C120N) in our prototype device. We are using it only to process streaming video. The FPGA plus a number of other components are going into the...
View ArticleAgain: MicroC/OS-II with the external VIC
Hi guys, I am still fighting with some issues that happen when using the external VIC. Here is what I have done: Nios II/f CPU with exceptions enabled, running at 125 MHz from external SSRAM. System...
View Articlejava.lang.Exception: No USB Blaster detected.
I am trying to use the Board-Test-System with a Cyclone V FPGA board and I keep getting this error. Another error I am getting that is possibly related is in the Programer software of Quartus II; I...
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