Multi IO voltage JTAG

My circuit is composed 4 Stratix4s per chain.

And each FPGA has multiple IO voltage. (see attachment picture)
Vccio of each FPGA's bank1A is connected to 2.5V.
So we connected pull-up to 2.5V.

But in my circuit there are no buffer or voltage translator.

I wonder my circuit conceptually is good for JTAG operation without level translator.

Regards,
JS Lee

Attached Images

• multi device jtag.jpg (118.5 KB)