Help, error occur during compilation. Can anyone help me please
Error list
175001 could not place fractional PLL
12289 an error occurred while applying the peripheryconstraints. Review the offending constrants and rerun the fitter
11802 cant fit design in device
Currently imusing the Altera PLL v13 to generate a clk signal 50Mhz to my d-ff.
Is this methodcorrect? Any other method? Because, I think the problem maybe due tothe Altera PLL v13 I use?
Current using the Cyclone v GX fpga dev kit & quartus IIweb package 13 software
Thanks J
Error list
175001 could not place fractional PLL
12289 an error occurred while applying the peripheryconstraints. Review the offending constrants and rerun the fitter
11802 cant fit design in device
Currently imusing the Altera PLL v13 to generate a clk signal 50Mhz to my d-ff.
Is this methodcorrect? Any other method? Because, I think the problem maybe due tothe Altera PLL v13 I use?
Current using the Cyclone v GX fpga dev kit & quartus IIweb package 13 software
Thanks J