Strange behavior of NIOS II IDE
Hello, I can't get my c code working on NIOS II processor, implemented on DE1. I'm using 9.1 sp2 ver. of NIOSII IDE. The same code with the same hardware sometimes works, sometimes not and the terminal...
View ArticleSATA Power Modes, C code problem
My issue is I read the value of ADI_DEV_CORE_STATUS it remains as 0x2A, even after I write assert a 1 on bit 22 to enable power mode requests, and i prit out the value directly after the value doesn't...
View ArticleUbuntu 13.04 : Can't connect to the Altera website to check for license file...
I have just install Quartus II (32-bit Version Buid 178 05/31/2012 SJ Full Version) on my Ubuntu 13.04 and have the message "Warning (291002): Can't connect to the Altera website to check for license...
View ArticleI think my FPGA is dead, I need help : (
I made a FPGA board with a Cyclone III and a EPCS64 over a year ago and always work well, I give it to someone for a couple of days and didn't use it until now and when I try to configure it says:...
View ArticleDE2-115 board and SD cards
Dear all, I am lookking for a way to save a big amount of data using DE2-115 board. I hesitate between USB Hard drive and SD card. I think SD card may be the simplest way, but the SDXC which enables...
View ArticleHelp: how to write a 20ns delay on verilog HDL
how to write a 20ns delay on verilog HDL? simple example pls thanks
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Vectored Interrupt Controller VIC Respond if i take out Ethernet Connector RJ-45
Hello Friends I am getting Continuous interrupt on nios-II, and this interrupt handle by VIC (Collected by edge_capture register-Please see attached jpeg ). whenever interrupt come i assert HIGH to...
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DDIO bitclock location and clkctrl blocks
Hi I'm using a Stratix III EP3SL340 C3 (Terasic DE3) and I had a question about DDIO and where to place the bitclock with respect to data. And if I should route it via clkctrl blocks. I have 12 bit...
View ArticleCyclone IV GX Transceiver GPIO
I'm using the Cyclone IV GX transceiver starter kit. Is there a way to use the LCD header pins as individual GPIO's ? The only alternative I see would be to remove user LED's or PB's and use them. Any...
View Article2 digit seven segment display
hey everyone, I am trying to write a code in verilog which should display from 00 to FF on seven segment. i have two segment display on my fpga board. It will be great if somebody can help me with code...
View ArticlePCIe IP with 2 VCs, Vendor ID only on VC0?
Hi All, I have a designed an SOC with a PCIe RootPort. It works fine. I just changed the PCIe IP to a 2 VC version. As a simple test of the second VC I tried to read the vendor's ID but I get no...
View ArticleQsys- BFM Testbench causing add_connection error
Hello- I'm having difficulties generating a testbench in Qsys. I have a system, comprised of a custom model, several altera stream test generator/checkers, and a few exported signals (among them,...
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SDRAM problem on DE0 EP3C16F484C6
Hi, I am using DE0 - EP3C16F484C6 board and have timing issue with SDRAM. When I interface SDRAM in Qsys, it generates Qsys successfully and also compiles on Quartus with some timing errors. When I...
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question about DM9000A project
Hi guys, I got a project about DM9000a on DE2 board using hardware design. I use the document from Tampere university as my reference which is put in the attachment. Basically I have finished 2 block:...
View ArticleDIMM Design
Hi, I'm new to Altera products and am looking to design a Dimm. It will need to connect to a PC motherboard and act as a proxy to a DDR2/3 device. The design can record memory accesses for analysis or...
View ArticleThread-Aware Debugging
Hi, In n2sw_nii52008.pdf page 10-3 is written that the Nios debug tools allows you to perform thread aware debugging when debugging a MicroC/OS-II application. The debugger can display the state of all...
View Articlesame configuration file across all the migration devices
Can I use the same configuration file across all the migration devices? I have two additional migration devices selected in quartus project. All of them are the same device with difference speedgrades....
View ArticleHELP, how to store data into the memory(example flash or any memory on my fpga
Topic: HELP, how to store data into the memory(example flashor any memory on my fpga dev kit) and read out the data when needed Example my is data is 4 bit 0110, 0111,0000 Anyone can advise me how to...
View ArticleIssues with Interlaken PHY on Stratix V
Hello, I am implementing a multi-lane Interlaken PHY design on a Stratix V part. There seems to be a dearth of documentation and experience regarding this IP. Specifically, I see some strange behaviors...
View ArticleError when generating hardware from .aoco file
I am trying to synthesize a kernel for a nallatech 385 board (pcie385n_d5) using the OpenCL toolchain 13.0. I am using the two step approach with the first step generating the .aoco file and the next...
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