PCI Compiler design
Hi, I am studying on a PXI card , I made a simple project but I have problem with made driver for it.It has 2 BARs and when I connect my card to PXI chasis , It is recognized from PC as a PCI device...
View ArticleUse PCI avalon compiler in QSys.
I want to use PCI in our design, but the PCI compiler seems not working for Qsys in Quartus II 13.0. At the same time, SOPC Builder has been disabled in the latest Quartus. So I tried SOPC Builder (in...
View ArticleModelSim and filename length limit
Hi, I'm currently trying to simulate the Hard memory controller example, and the files in "vhdl/submodules" are very long. For some reason modelsim fails to read any of the files with filenames greater...
View ArticleCyclone V LCD / I2C (baremetal) sample for Altera's SoC DevKit
Hi community, anybody out there ever programmed the Newhaven LCD on the Altera SoC (Cyclone V) DevKit baremetal? If I didn't miss something Altera's hwlib doesn't provide support for I2C (not to...
View ArticleTurn on 4 leds nios II
hello, I have a FPGA Cyclone III ep3c25. I use NIOS II, I turn on the first LED. Now how to turn the 4 LEDs. i use this code to blink first led. Code: #include <stdio.h> #include "system.h"...
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TSE gets the wrong local loopback and received data!
The software I am using is quartus ll sp1 11.0. The device I am using is EP4CE15F17C8. TSE was configered shown as below: 9.jpg I just want to use the TSE to control a 100Mbits PHY. A simulation...
View Articlecyclone V static power
We recently designed and built a new PCB with a Cyclone V part on it. The part we used is 5CEFA7U19I7N. We are seeing static power consumption that is around 4x the "typical" amount predicted by the...
View ArticleCannot Compile Vector-Add Example
I'm having trouble simply compiling the examples in the opencl sdk. I've tried the vector add as well as the moving average. The log from the vector add is below, any advice on how to solve the error...
View ArticleJTAG Chain xd2000i
Hi everyone, Does anyone remember xd2000i? SAN JOSE, Calif., June 17, 2008—Altera Corporation (NASDAQ: ALTR) and XtremeData, Inc. today announced availability of the industry’s fastest FPGA/Intel®...
View ArticleSelection of high speed ADC and FPGA
Hello, I'm new to the FPGA world and I'm looking for the right FPGA evaluation kit that can interface with a high speed ADC with at least 6 channels and 100MSPS. I've found the linear technology ADC...
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SI analysis of Cyclone V with LPDDR2
Dear All, I'm conducting SI analysis of Cyclone V with LPDDR2 (Micron MT42L32M16D1AB-3). It is observed that there is a problematic ringing phenomenon on the edge of waveform. waveform.jpg I'm using a...
View ArticleNeed help for schematics PSK modulation on Stratix II
Hi, i'm a student of university and i need help for a project for a exam. The target is the implementation of BPSK (binary phase shift keying) modulator on FPGA Stratix II with the MegaCore Function in...
View ArticleNallatech PCIe385 driver problem
I have a PCIe385 (not PCIe385N) board from Nallatech. The Linux driver in the 13.0 AOCL release does not seem to recognise my card. lspci says: 01:00.0 Unassigned class [ff00]: Altera Corporation...
View ArticleCylone V IBIS File Availability
I don't see the Cyclone V IBIS files available for download on the IBIS models page. Can someone point me to where they are available for download?
View ArticleVein Pattern Recognition using DE1 board
Hello Friends, I am working on a project for Vein Pattern Recognition using Altera DE1 board. I have used a modified IR webcam for capturing the vein patterns. I have some doubts regarding how to...
View ArticleExternal and Internal TBI PHY
HI, I want to configure my Ethernet controller in sgmii mode(rgmii is working).As sgmii requires configuring TBI PHY and also external Marvell PHY and also Ethernet controller.Can you please guide me...
View ArticleopencoreI2C for cyclone3
Hi I am implementing opencoreI2C, can some one double check my code. I am new to opencoreso I am having problems in figuring out scl and sda. Here is my code #include <stdio.h> #include...
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Chip-planner block names inside the PLL
What do these two blocks indicate in the chip-planner? PLL DPA Output and PLL LVDS Output Anybody know of a link to Altera's documentation on this kind of information related to the chip-planner? E.g....
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ROM at ModelSim - data port is in High-Z State
Hi all. Im new to FPGAs. I have built some circuit with ROM memory (added with MegaWizard). The problem is memory output port is in the High-Z state all the time. I have connected clock to 50M clock,...
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Video buffer/rate matcher
A picture is worth a 1000 words. what am I looking for ?? SDRAM, VRAM, SRAM, RAMmyhead, should I be looking for ?? My implementation is what is called a ''data buffer'', all data is write and read...
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