Connection the Internal Oscillator to the PLL Input Clock in Cyclone III
Hello, I was wondering if it is possible to connect the internal oscillator to the reference clock in a Cyclone FPGA. It just wouldn't synthesise when I tried it earlier today. It gives the following...
View ArticleMake file error in eclipse called from Quartus
1. Make file error 2. after programmed to board using verilog file, all lights are on no matter turn on or off switch, is it due to test bench module in top level file? will it affected c language file...
View ArticleHDL with Quartus 10.0 (state machines and counters)
Hi Forum, I am not sure if this the right forum. I am working in a project in which part of the code was written in HDL. There is a state machine, SM, which changes states according to some counters....
View ArticleDDR Memory IP for Bemicro SDK
The BeMicro board has a quite a few components that aren't instantiated with the accompanying project files. Aside from the SD Card and ethernet, the ddr memory is especially interesting.. at the...
View ArticleNios II boot Remote Update
I'm working on the Nios II with the device cyclone III, my flash EPCS64 memory contains 2 FPGA images and 2 softwares. The 1st FPGA image (factory) address is 0, the 1st Nios software address is...
View ArticleData storage in DE2-115
Hi, I have two signals that are to be compared. One of the signal would be real time which will be sent in through one of the input ports. I intended to store the other signal in the evaluation board...
View ArticleQsys Generation: NullPointerException
Hello,I'm reasonatly designing a portation of ARM's Cortex-M0 on an altera fpga. I've got a problem with using qsys system integration tool: When i try to generate the system, the generation exits with...
View ArticleUbuntu 13.04: Segmentation Fault during MegaWizard ALTDDIO_OUT creation
Hardware: DE2-115 development board (Cyclone IV) OS: Ubuntu 13.04 64-bit I'm trying to follow the Triple Speed Ethernet tutorial (I can't include the link, but it's "using_triple_speed_ethernet.pdf" on...
View ArticleNios_II UDP Offload example Frame error
Hi all, I'm using udp_payload_inserter part of UDP Offload example to send frame from TSE to PC. The PC application (c#) receive frame only when i'm running wireshark!!! I think that the frame does not...
View Articleif else statement in Verilog
I used to do a lot of C/C++ programming, and I do like to use for loop and if-else statement. 1. I tried to use if-else in Verilog. However, I always got an error which said that --- near text "if",...
View ArticleUART RS232 receive missing bytes
Hi, I have trouble receive bytes of data using UART RS232 port on uClinux running NIOS2 /f. A loopback application was implemented to send 128 bytes hex data from ttyA0 (RS232 port) and receive on...
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FPGA : Cyclone 1 Orcad problem
I am absolutely new to FPGA devices, so please excuse me for novice questions. I am designing a FPGA board using EP1C12Q240C8 of cyclone 1 device. I am using orcad capture for designing the schematic....
View ArticleNand flash controller with avalon interface
Hi, I am working on a project which require AVALON interface to a nand flash device. It will be of a great help if someone can guide me in the right direction. regards, abhinavpr
View Articlehow can i use the optional embedded PMA for Cyclone V GX device?
I would like to use the SGMII interface between cylone v GX device and the PHY device for communication with a PC. I could generate a TSE ip core mit PCS interface. So I need the PMA module for...
View ArticleNios II interrupt design example required
I want to understand how to write code for a timer interrupt for the NIOS II in Eclipse. I understand that this will require me to use a timer block in Qsys and than use it to generate the interrupt...
View ArticleUsing FFT Megacore function in QuartusII project itself
Hi all, I just want to know if it is possible to use the VHDL code generated in MegaWizard Plug-in manager's FFT Megacore function in a QuartusII Project and program an altera DE2-115 board. Say I have...
View ArticleHow to get Cyclone IV GX dev board to auto-load user design?
I have been pulling out my rapidly dwindling hairs trying to figure out how to get the dev board to power up and boot my design and not the factory load. Following all the directions in the manuals got...
View Article2D array with different number of elements
Is it possible to have this array in VHDL? [i][j] = [1][sample1, sample2, sample3] [2][sample1, sample2, sample3, sample4, sample5] [3][sample1, sample2] It seems like [j] dimension has to be a fixed...
View ArticleYocto for Cyclone V
current Yocto release for Altera Cyclone V is the Danny release. When will there be a Dylan release? Thanks, Kirby
View ArticleUpgrade to newer QII from QII 9.1 SP2?
Hi there, Most of our design projects are still on QII 9.1 SP2 and we are looking to upgrade them to the latest and greatest. One problem we found in this migration process, is the resource usage of...
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