Converting FPGA design to VLSI design

I have a design which has been verified on Alter FPGA. Now I'm going to convert this design to VLSI design. I will use Cadence RTL Compiler for synthesis and SOC Encounter for route and placement. However, I use some IP Cores in the original design including FFT, multipliers. Can I synthesize and route the IP Cores with RTL compiler and SOC Encounter, respectively? Does anyone know the step?


Thanks!