why usb blaster need be set a max3378 （Level conversion chip）
i have seen the altera usb blaster ，there is nothing Level conversion IC ，but others always said that it should be a Level conversion ic in the usb blaster to fit the different Level of the target...
View ArticleSymbol Files
Hi, I use symbol files as the TOP Level of my VHDL designs as it gives a nice visual representation of the modules. I usually edit the block to make the schematic flow logical. However if I change one...
View ArticleAltera De4 board PCI not recognized
Hi, I am programming an Altera De4 - stratix IV 530 board with some OpenCL codes on a windows 7 64 bit machine, however the Altera board is not showing up as an Accelerator device. It is just showing...
View ArticleConverting FPGA design to VLSI design
I have a design which has been verified on Alter FPGA. Now I'm going to convert this design to VLSI design. I will use Cadence RTL Compiler for synthesis and SOC Encounter for route and placement....
View ArticleConverting FPGA design to VLSI design
I have a design which has been verified on Alter FPGA. Now I'm going to convert this design to VLSI design. I will use Cadence RTL Compiler for synthesis and SOC Encounter for route and placement....
View ArticleWeird VHDL Multiplier Problem
Hello all, I was recently given reign over a DE0-Nano board by my research adviser to turn into a interference fringe counter of sorts but I am having some problems programming multiplication in VHDL...
View Articleu-boot compiling problems custom NIOSII based board using cyclone III
Hi, I could not find a specific forum for u-boot on NIOSII so i hope this is a good place to start. I have a custom board that uses the Cyclone III FPGA that is running uClinux 2.6.38. I am trying to...
View Articlewarning: output pins without output pin load capacitance assignment
I know this might be very fundamental. However, when I assign a pin to an output, do I need to assign a load capacitance (pf?) to this pin? Or maybe the tool will do it for me? Thanks.
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Nios2eds can't detect usbblaster
My os: Ubuntu 12.04 lts After I configured the .sof file for my de1 board, I tried to program the "hello_world_small" template to the board but i got "No Nios II target connection paths were located....
View Articlewarning: connected to dangling logic and will be removed
I have the output port width of 12 bits, and the intermediate result is of 14 bit width with the first 3 bits being sign bits (result of 3 addition). I need to remove the first two sign bits (no...
View ArticleStrange error message during kernel execution: "No kernel updates in a while..."
Hi all, I'm observing a strange error message during kernel execution on nallatech-pcie385n-d5 "No kernel updates in a while... a kernel may be hung" It comes with a list of kernels (kernel1, kernel2,...
View ArticleGenerate the VHDL/verilog from a simulink model consists with AlteraDSP blocks
Hi, Pls let me know how can I generate VHDL/verilog files from simulink model that consists of AlteraDSP components. Thanks
View ArticleCyclone V SX Component for Altium Schematic Design
Hi Currently i'm designing a board using the new Cyclone V with HPS -> the SX version (5CSXFC6D6F31C8NES - same as on the Dev Kit). To develope the schematic and PCB i need the Cyclone V SX...
View Articleuse mif file to initialize mem
Are there any tutorial about how to create a mif file via file->new->mif from the tool bar? For example, If I need to initialize RAM/ROM with addr value 0 00 1 01 2 11 3 10 how should I choose...
View Articleunregister altsyncram ports
Is it possible to unregister input AND output ports of altsyncram in Cyclone IV E ? how? thanks for helping me... :)
View ArticleQuartus-Qsys-BSP issue
I have a design that contains 2 instantiations of a DDR3 controller. Once controller is connected to the NiosII via an Avalon MM bridge (NiosII-->Avalon.MM.Bridge-->Uniphy DDR3 controller) and...
View ArticleTerasic de4 Stratix 4 not showing up as an accelerator
Hi, In the device manager my stratix 530 de4 fpga is not showing up as an accelerator. It is showing up as Terasic PCIe FPGA BOARD under jungo in the device manager.
View ArticleAlmost Working: USB ISP1362 DE2-115 without NIOS II
I think I'm almost done with this damn thing. I think I can see the light at the end of the tunnel. I'm sure it's just another freight train, though. So, I've interfaced with the ISP1362. I have set...
View Articleexternal pull-up resistors
I am working on an old design using an EXP880. I have an output pin which I need to be high during power up. Is there a recommended value for external pull-ups, or can you program an internal pull-up?...
View Articlehow to read the memory initialized by "lpm_ram_dq"
If I have a block of memory initialized by an instance of lpm_ram_dq. // instantiating lpm_ram_dq lpm_ram_dq ram (.data(datain), .address(addr), .we(we), .inclock(inclk), .outclock(outclk),...
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