Phase reconfig control register altpll on cycone iv
Hello, I´am trying to get the dynamic phase shift for altpll run. Therefor i have two pll´s and i want to shift one of them with register Phase reconfig control register from document Embedded IP page...
View ArticleDifferences in NIOS versions 11 to 12
I am new to the NIOS development so please bear with me. I have inherited a legacy product (over a megabyte of source) where the former developer is not available for consultation. The software system...
View ArticleBTS not detecting device
Hi, I am trying to run the board test system for the Arria V development kit on windows 7 and I keep getting the error message of Connecting to the target...java.lang.Exception: Could not find device...
View ArticleCommunication Board/Computer
Hello everyone, I would like to make an application on my computer like the demo Control_Panel. My aim is to use my DE0-Nano board to get informations from differents sensors (temperature,humidity,...
View ArticleFailure to Release cl_mem buffer?
My code is looping through a few different kernels (each is very similar, just compiled with a few different optimizations) and I am trying to avoid the overhead of copying live buffers back to the...
View ArticleConstraining ripple clocks, clock mux output clocks, altddio output clock
Hi I have a design in which I send out (off chip) (inverted) "sysclk_out" from altddio. I do not use PLL as a source clock. I just use the incoming clock (sysclk_in) to drive the altddio. a.) I could...
View ArticleFrame Buffer VHDL Template
Hello every body, I'm trying to code a frame buffer using VHDL to perform some operation on an entire frame then store the result into DDR2 memory. I used the Avalon MM Master VHDL Template but I...
View Article!!!! Read Me !!!!
This forum is still under construction so if you post here in the meantime make sure your post is very clear on the topic so that I know which subforum to move it to later.
View Article!!!! Read Me !!!!
Posts to this forum should be about the hard processor system (HPS) or the interaction between the FPGA fabric and HPS in the Cyclone SoC devices. If you have generic Cyclone questions that are...
View Article!!!! Read Me !!!!
Posts to this forum should be about the hard processor system (HPS) or the interaction between the FPGA fabric and HPS in the Arria SoC devices. If you have generic Arria questions that are applicable...
View Article!!!! Read Me !!!!
This forum is where you can ask question about the hardware libraries (HWLibs) for the SoC devices. The hardware libraries consist of the SoC abstraction layer (SoCAL) and the hardware manager. Please...
View ArticleHunting down a stuck port?
Anybody have suggestions for why a port might be stuck? I can see in the RTL viewer that Quartus has replaced my inputs with 0. However, I don't know why. Everything up to that block is fine in the RTL...
View ArticleThe ModelSim cannot simulate the design contain lpm_dff
I had made a design include lpm_dff(lpm_dff.tdf) and try to use ModelSim-Altera 10.1b to simulate it. In Modelsim project not only the testbench file and the design file were added, the altera_mf.v and...
View ArticleQuartus (13 or 12) on Ubuntu 13.04 64 bits - device go constantly offline
Hi, my Quartus II is able to recognize my device. If I go to Tools -> Programmer, select my hardware, the .sof file and click start. It works. However, If I go to Signal Tap II and try to download...
View ArticleThe Problem when simulate the lpm_ff using ModelSim-Altera
I am a new learner for ModelSim, and I have met some problems about it. I have made a simple dff using lpm_ff, the code is showed below module FDDF(clk,clear,q); input clk, clear; output q; lpm_ff...
View Articlecalculator
Im doing a project that requires a calculator using the keyboard as an input and my deadline is tomorrow so if anybody could send me a code to help me in this project its required to be written with...
View ArticleNAND Flash controller for Cyclone V E family
Hi, I would like to use a NAND flash component on my design with a Cyclone V E FPGA and having trouble to use the generic tri-state Mega function to work with it. The NAND flash component I selected is...
View Articleverify failed between address 0x3000020 and 0x300988B
Hello, When I build and download my Hello World application using the 'Run Configurations' GUI menu in Eclipse, I get a 'verify failed' error. Anyone know what this indicates and how I can resolve...
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