Dear specialist:
My design is shown down, it can run accurately in EP3C120F484I7.
I will transplant it to 5AGXBB3D4F31I5N, I cant determine if it may be affected by the Fractionan PLL Phase Alignment Error listed in <Errata Sheet for Arria V Device> .
The chip AD9653BCPZ-125 is followed by the FPGA and the FCLK is 93MHz.
Please help me，,thanks a lot 22.jpg
My design is shown down, it can run accurately in EP3C120F484I7.
I will transplant it to 5AGXBB3D4F31I5N, I cant determine if it may be affected by the Fractionan PLL Phase Alignment Error listed in <Errata Sheet for Arria V Device> .
The chip AD9653BCPZ-125 is followed by the FPGA and the FCLK is 93MHz.
Please help me，,thanks a lot 22.jpg