I spent a bunch of time fighting with this issue so I thought i would share.
I am using Quartus 13.0sp1 and Bemicro SDK development hardware trying to make a simple nios ii system work.
I went through the Bemicro hardware lab tutorial (written for quartus 11) but when I attempted to connect to nios in eclipse it would complain that it could not find a valid sysid or timestamp for the hardware and the nios would not run. After much troubleshooting I discovered that the PLL (Avalon altpll in qsys) that was driving the nios ii clock was not running. The PLL seemed to be hooked up correctly and the input clock was running but no clocks were output and the lock bit was low. To fix the problem I had to export the areset conduit and tie it high.
The part that is not intuitive is that in the ALTPLL wizard I unchecked the box to generate the areset input. According to the documentation this is an optional input that in typical systems you do not need. However with the avalon altpll in Qsys apparently even if you uncheck the box to generate the asynchronous reset, this signal still gets generated and you must export it and make sure it is tied high.
I hope this helps someone.
I am using Quartus 13.0sp1 and Bemicro SDK development hardware trying to make a simple nios ii system work.
I went through the Bemicro hardware lab tutorial (written for quartus 11) but when I attempted to connect to nios in eclipse it would complain that it could not find a valid sysid or timestamp for the hardware and the nios would not run. After much troubleshooting I discovered that the PLL (Avalon altpll in qsys) that was driving the nios ii clock was not running. The PLL seemed to be hooked up correctly and the input clock was running but no clocks were output and the lock bit was low. To fix the problem I had to export the areset conduit and tie it high.
The part that is not intuitive is that in the ALTPLL wizard I unchecked the box to generate the areset input. According to the documentation this is an optional input that in typical systems you do not need. However with the avalon altpll in Qsys apparently even if you uncheck the box to generate the asynchronous reset, this signal still gets generated and you must export it and make sure it is tied high.
I hope this helps someone.