Can I get a checksum from a Max V via JTAG>
We use .SVF files to program the MAX V on our board using the on board microprocessor via JTAG. This is to allow remote updates. The guy coding the uP has asked me if there is any way to obtain the...
View ArticleQuartus SoC Compiler Warnings
When an SoC design generated by Qsys is compiled in quartus there are a bunch of warnings generated. In the training classes they always tell us to ignore these warnings. In general, I like to know the...
View ArticleFIFOED UART in QSYS
I am using qsys version 13.0 sp1 for building a design. My target device is Cyclone V. There is a FIFOED_UART module intergarted in my design. When I press generate I see this error: generatin callback...
View ArticleSome problem about CPLD EPM570
Hello, I have some problems about EPM570. What's the GCLK maximum value that could be accepted? I searched datasheet and found it can input higher than 100 MHz. But I input a 100 MHz XTAL and CPLD...
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timing constraint for clock mux and how to set output delay
Hi all, I have to constrain the output pins of my design by using "set_output_delay." The reference clock for those outputs pins comes from a clock mux. I've check the following link to know how to...
View ArticleIORD_ALTERA_AVALON_PIO_DATA execution speed
Is there a faster way to read a pin than using the IORD_ALTERA_AVALON_PIO_DATA macro? I'm finding the code below is running quite slow, but by removing the second condition (i.e. reducing the number of...
View ArticleByte order in RBF file
I'm trying to load a device in FPPx16 mode. As the code reads a byte at a time from the RBF file, is the first byte the lower 8 bits or the upper 8 bits? Do I need to flip the order of the bits? Thanks!
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Schematics to configure Cyclone GX by Parallel Flash Loader (MAX II+NOR Flash...
I am looking for schematics for a stadard solution. I need to configure Cyclone IV GX in PS mode by Parallel Flash Loader residing inside MAX II with configuration data inside NOR Flash Memory. Please...
View ArticleClock and Gain (Width) in VHDL
Hello friends, recently, i have been asking questions on this forum. Pls dont get upset at my questions if they are too elementary. This is because i'm new to this area and i've got a deadline for my...
View ArticleProblem with JTAG indirect
I am trying to configure a EPCS1 through JTAG indirect. I receive the following message, which is as cryptic as the help. Serial Flash Loader Active Serial Memory Interface on device 1 is not granted ....
View Article64 bit DMA for memory to custom component only transfers 32 bit!
Hi, I am using QSYS and am trying to transfer the contents of a memory component to a custom component with a DMA. Both memory and custom component have a data bus width of 64 bit, and the DMA is...
View ArticleDynamic hand gesture recognition
Hi i am working on a project that using hand gesture.I am looking for a simple algorithms to translate the Dynamic hand gesture to meaning full action for system. There is so many algorithms in...
View ArticleQuirkiness with avalon PLL areset in Qsys
I spent a bunch of time fighting with this issue so I thought i would share. I am using Quartus 13.0sp1 and Bemicro SDK development hardware trying to make a simple nios ii system work. I went through...
View Articlecan i declare a 2D array as following ?
hi every body can i declare a 2D array as following ? Code: type dataout is array (6 downto 0,11 downto 0) of std_logic_vector(7 downto 0); i guess this is a 3D array not 2D. so how i can have a 2d...
View Article3D array
hi every body can i declare a 2D array as following ? Code: type dataout is array (6 downto 0,11 downto 0) of std_logic_vector(7 downto 0); i guess this is a 3D array not 2D. so how i can have a 2d...
View Articlehow to simulate custom instructions
My multi-cycle custom instruction is not behaving as expected, the problem is also, that the exact timing of the interface signals from nios-2 is not specified in the Altera documents, is there a way...
View ArticleError (10170): Verilog HDL syntax error at sha256_pipe.v
Hello all, I got the following error while trying the Verilog HDL. I'm using Quartus II 13.0. Error (10170): Verilog HDL syntax error at sha256_pipe.v(89) near text "["; expecting "}" Error (10170):...
View Articlehow could i get two tse mac with two phys on DE2-115?
i tried to use both of the phys on DE2-115, so i add two mac, two sgdma_rx, two sgdma_tx, two descriptor_mem, and one cpu in Qsys. and i changed the top level file, in order to use both of the phys....
View Article[.tmp_vmlinux1] Error 1
Code: LD .tmp_vmlinux1 /home/student/nios2-linux/toolchain-mmu/x86-linux2/bin/nios2-linux-gnu-ld:arch/nios2/kernel/vmlinux.lds:197: ignoring invalid character `#' in expression...
View Articlekeeping bdf and verilog synchronized
Hello all One nice feature of quartus II 13.1 is the creation of bdf (Schematics) files in a visual form. However, it may happen that you wish to convert you schematics to Verilog to add pieces that...
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