Hello all
One nice feature of quartus II 13.1 is the creation of bdf (Schematics) files in a visual form.
However, it may happen that you wish to convert you schematics to Verilog to add pieces that are easier defined using a text editor
This can be done using File -> Create/Update -> Create HDL design from Current file
Once you have changed the verilog, is there any way to synchronize the original bdf with the updated verilog ?
As far as I can tell the File -> Create/Update menu has no option for this, am I missing something ?
Thanks, Damiano
One nice feature of quartus II 13.1 is the creation of bdf (Schematics) files in a visual form.
However, it may happen that you wish to convert you schematics to Verilog to add pieces that are easier defined using a text editor
This can be done using File -> Create/Update -> Create HDL design from Current file
Once you have changed the verilog, is there any way to synchronize the original bdf with the updated verilog ?
As far as I can tell the File -> Create/Update menu has no option for this, am I missing something ?
Thanks, Damiano