Smart compilation option is disabled for Arria V GT series?
Hi I want to modify memory content without compiling the complete project. But when I try to use 'Rapid compilation' option in "Settings-Compilation Process Settings-Incremental compilation- Rapic...
View ArticleFailure of STL map "insert()" (VxWorks v6.8). ... MIPS
A_MAP.insert(std::pair<uint16_t, THE_STRUCT_TYPE>(Key, A_STRUCT)) A_MAP[Key] = A_STRUCT; Both methods work on Visual C++ Express 2012. Both methods fail on VxWorks at run-time with Signal 11....
View ArticleCyclone V Transceiver Synchronised 32bit Word Alignment Problem
I am using the Cyclone V GT demo board in an attempt to get a transceiver channel that has a direct loopback (Tx->Rx) across the HSMC to verify a physical link running and synchronised correctly at...
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Read back PIO output status
I have a Qsys PIO component that is 7 bits wide. It is configured as an output (it drives 7 LEDs). I would like to be able to determine which bits of the output are set and which are cleared (or...
View ArticleMaxV IO voltage compatibility
Hi everyone, I am working on a MaxV design that needs IO compatibility with ICs that will be powered from 2.3V. Looking at the MaxV datasheet and the pin configurations in Quartus I am led to believe...
View ArticlePain or no pain with Cyclone V Integrated ARM?
Hello, I've been reading about the new Cyclone V and it's integrated ARM processor and wanted to ask if anyone would share their comments about the device. I would like to know how easy is it to get...
View ArticleFailed to post DMA transmit request
Hi, I tried to use the general Avalon-MM DMA controller in Qsys and use the following C code to implement the DMA transmit: Code: #include <stdio.h> #include "system.h" #include "io.h" #include...
View ArticleQuartus II 13 synth. a SV comp. which uses an interface and attach to...
Hi, I've looked around on this forum and google, but have come up empty. (There may be a keyword I'm missing but I am here now:) I have a component of a larger design that I want to synthesize and...
View Articlenot able to update memory content (.mif files) using 'update memory...
Hi I am using Quartus v12.1. I have read in many relevant threads that following steps can be taken to update .mif file content. 1. change .mif file(s) 2. select Update Memory Initialization File in...
View Articlemulti dma request how to arbitrate
hi , now i encounter a problem in my project, there are multi TS data request dma to transfer data to the same ddr，but only there is one dma to handle the requests, how to find which channel is request...
View ArticleHow to load programming code to ROM of Cyclone III Video Development Kit?
Hi all! I am a student and doing a project a project about Video and Image Processing on Cyclone III Video Development Kit. I have read many document about this kit to find out how to load programming...
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Tightly Coupled Memory-Use
Hello Friend's For getting better performance on nios-ii one can use tightly coupled memory for both data and instruction. i have done the following 1. Add the Tightly Coupled Instruction and data port...
View ArticleSilent/Unattended Install Quartus II Subscription Package 13.0 SP1
Hello, i have problems with the silent installation of Quartus II Subscription Package 13.0 SP1. I must install the software at three pc pools. QuartusSetup-13.0.1.232.exe" --mode unattended...
View ArticleSOPC clock from dynamic reconfigured pll
Hi all, I try to do the following and would like to ask if this is absolute nonsense before I start . . .:confused: I have Quartus 9.1 SP2, a Cyclone III FPGA, and a Nios II SOPC up and running at a...
View ArticleCyclone V SX SoC dev board - AHB
Hello, I am using the Cyclone V SX SoC development kit and I need a connection to the ahb bus. At first I must connect an AHB slave and then an AHB master. I'm new to qsys. I have connected the h2f_axi...
View ArticleLooking for schematic symbol for Cyclone IV EP4CE75 780 BGA
I have been able to find the symbol for the smaller foot print, however, the larger foot print is needed. Does anyone know if this exists and where to find it? Altium or OrCAD are preferred.
View Articlesignaltap erroneous trigger
I have the trigger set for rising edge on a bidirectional FPGA pin. My oscilloscope does not indicate a trigger and the signal is constantly low, but signaltap is indicating a pulse is present.
View Articleextract list of time-limited IP licenses from quartus project
I need a way to build a list of all the required IP Licenses in a Quartus project. I have a design in the NEEK that I need to be able to boot from flash. To do this, I need licenses for all the...
View ArticleGood way to generate /WE signal?
Hi all! Does anyone have any suggestions for generating a (negative-logic) write-enable signal for an async ram? The ram I'm (planning) to use has a 0ns data/address hold time and since I'd like to...
View ArticleChanging Nios Clock Frequency on a De0 nano board
Hi, I've got a design including a Nios 2 working on my De0 nano board. I read the tutorials for setting up a Nios 2 in Qsys, I just added some more pio for my signals. I'm also using the SDRAM, so I am...
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