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Gigabit Ethernet Interface (via Marvell 88E1111) with Cyclone IVE FPGA

Hello Everybody, I am using Altera DE2-115 Board (CyloneIVE device) and want to connect some other device running in Gbps via its Gigabit Ethernet Transceiver (Marvell 88E1111) interface. Can I get...

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mSGDMA stride reads/writes

Has anyone used the Stride feature (available with the extended descriptor)? I using the Qsys PCIe example design on the wiki. When I enable the extended descriptor and stride option, the data transfer...

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Searxhing for a Cyclone III guru

Please note I am new to this forum so if my post is in violation of any rules - please forgive me We are a HW startup in SF. We have a system that uses an Altera Cylone III dev kit. We need someone who...

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Constraining a source synchronous, SDR, center aligned Input

I'm running mad with this: I want to connect a Texas Instruments TLK2201 to my FPGA (Cyclone IV). This Ethernet-Serdes has got a Ten-Bit-Interface (TBI) with center aligned Data at 125MHz. The Data are...

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Basic Verilog questions: sequential execution within a procedural block

Code1:always @ (*) begin<delay1> out1 =/<= a && b;endalways @ (*) begin<delay2> out2 =/<= c || d;endalways @(*) begin<delay3> final_out =/<= out1 || out2;end Code...

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Can I update memory content by changing .mif files without compiling whole...

I am working on a project which uses arria V version and I want to update RAM memory content just by replacing .mif files. I have a demo which contains .qip and .v files generated by MegaWizard Plug-In...

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Updating the flash PCIe-385N board

Hi, When a PCIe-385N board is purchased and shipped directly from Nallatech, the flash is loaded with a default FPGA program compatible with the latest version of the OpenCL SDK tools. In other words,...

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DE1 Basic Computer on Nios II SBT

Hi everyone! I am a beginner with the Cyclone II board. Just got it last week. I tried to implement the DE1 Basic Computer project with the Altera Monitor Program and it works absolutely fine I wanted...

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DE1 Basic Computer on Nios II SBT

Hi everyone! I am a beginner with the Cyclone II board. Just got it last week. I tried to implement the DE1 Basic Computer project with the Altera Monitor Program and it works absolutely fine I wanted...

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Altera Stratix iii- Generating voltage swing...

Hello friends, Am a student new to Quartus and Altera devices. Am working on my project and it would require an unstable voltage supply (at START) to my stratix III FPGA. This i will compare with a...

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problem on loading .jic file in epcs64

hi all, i am using epcs64 flash in my design, and it is in AS configuration. when i try to program the flash, for the first use the loading of image is success.And if i'am changing the image files or...

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to Port JRunner or Jbc Player

Hello all! I am working on configuring FPGA in JTAG mode using an 8-bit MCU--8051. I‘m not sure to port JRunner or the Jam-Byte Code Player ,and I am confused in "How to port these c program to my...

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Logic cell count is missing in project navigator window for some components...

Hi All, I am very new to this area of working and i have got stuck up at some points. I do compliation for the entire project. After successful compliation, i could see that logic cells count for some...

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issue installing Quartus-web-13.0.1.232 on win 7 64 bit

i have a problem installing Quartus-web-13.0.1.232 on my win7 64 bit every time I'm trying to install it I'm getting a msg that "Quartus-web-13.0.1.232 has stopped working" and the options are to debug...

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USB blaster driver install without board

Hi all I would like to be able to install the USB blaster driver (Quartus II v13) without a need to plug in the board. The purpose is for unattended installation for the university. Is this possible?...

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SystemC Simulation using Modelsim Altera web Edition 6.3g_p1

Dear sir, I am using Modelsim Altera web edition 6.3g_p1. We would like to use it for systemC based designs. When we try to do the simulation of a simple system C file (following code), it compiles the...

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ModelSim Hazards Issue

Hello, First, thank you for taking the time to read this post. I am currently in the simulation stage of development of a VHDL design that uses a RAM block (M9K) to generate a histogram. My test...

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Resistors on DE2 board switches

I have a question about the resistors which are connected from SW13 to SW17, but the SW0 to SW12 are directly connected to FPGA in DE2 board, like in DE2-70. Anybody knows why? In comparison, all...

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Is c2h over with Quartus 13.0 ?

Hi all, that's my first post here in this forum! :) Well, this is my question: is c2h over? it says in quartus 13.0 there is no way to download NIOS EDS legacy tools, and so NIOS II IDE; C2H is not...

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Active Serial restart after programming

Hi, I'm using an Altera USB-Blaster to configure my EPCS4 with Active Serial. I have a dual boot Windows / Linux system, both on which I have installed Quartus II 13.0 Web Edition. Now, in Windows when...

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