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Serious USB-Blaster Problem in Altera Monitor Program
Hi, I am trying to learn and use Altera Monitor Program. I am following the tutorials at the Altera University Program. These are very nice. I can use USB-Blaster for downloading bitstreams to my DE2...
View ArticleRT preempt patch for Linux 3.7
Hi! Is there anyone already having a rt-preempt patch running on the SoC? I'm not very familiar with Linux and found nothing about it on RocketBoards. What i need to know are the reachable latency...
View ArticleAltera / Softing EtherCAT solution
Hi! Has anyone already the Softing EtherCAT solution running on the Altera CycloneV SoC Develompentboard? I was able to get the Beckhoff IP - Core running and use the Beckhof Slave Code Stack with a...
View ArticleADC implementaion in DE2-115
Hello, I am newbe to FPGA, i have a query. We have DE2-115 developemntal board and like to know whether we can implement a ADC and EtherCAT interface. Do we have any documents or refrences about these...
View ArticleFun or no fun with Cyclone V Integrated ARM processors?
Hello, the following I have posted on another Forum but haven't receive many responses. So, I am going to post it here. I've been reading about the new Cyclone V and it's integrated ARM processor and...
View ArticleClock enable for MAX V altufm_none ignored in simulation
Moin, I'm using Quartus II Version 13.0.1 Build 232 06/12/2013 SJ Web Edition with the included ModelSim ALTERA STARTER EDITION 10.1d Revision: 2012.11. My project uses Verilog HDL and is targeting the...
View Article*** Read Me !!! ***
This SoC development boards section is intended for questions about the various SoC boards on the market. You can also find information on Rocketboards.org: http://www.rocketboards.org/
View ArticlePcie Address problems
I'm running the PCIE to external memory design(an431) on the cyclone 4 starter kit, and I'm confused with some address issues. 1. From the Qsys design, I can see the onchip mem start from address...
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Across clock domains problem
There are two main clocks in my project, one is 250MHz, antoher is 100Mhz. A counter counting according 250MHz clock. I want to register the counter's value at some conditions, and send this value into...
View Articlestratix IV on DE4
Hi guys, I have quartus v12.1 and recently purchased the DE4-530 board which has a stratix IV FPGA, I want to use sopc builder with ALTMEMPHY for the ddr2 sdram. I know i should use the uniPHY with...
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Simulation Alpha Blending Mixer IP core
Hi eveyone, i want to use Modelsim to simulation Alpha Blending Mixer. I create a control block with avalon-MM interface. But it's not working. :( This is block diagram and veirilog code...
View Articledividing to 32bit signed integers with ieee_fixed_pkg -> error
Hello everyone, I am trying to divide two 32 bit signed integer signals (see code below). I am using the fixed point package from bishop, which invokes the lpm_divide megafunction. When compiling the...
View ArticleConfiguration settings for StratixIV - DE4(230K)
Hi, I am currently trying to get the configuration from CFI Flash running. I am able to program the CFI Flash but the desired configuration is not getting loaded when the board is reset. I am currently...
View ArticleComplex dual tone generation
Hello, I am trying to realize a VHDL code able to generate a complex baseband dual tone signal. What i would like to to is then send this signal through the HSMC port to a DAC evaluation board, where...
View ArticleNIOS II Simulation Error
Hi again. I have a simple system with Nios II e, SDRAM, On-Chip memory, JTAG-UART and Sys-ID Peripheral. I created "Hello World" in the NIos II Eclipse IDE and it runs, I get "Hello from Nios II!" in...
View ArticleExample of Controlling a Stepper Motor using VHDL or Finite State Machine
I am new to Altera. Does anyone have an example I can follow for controlling a stepper motor? I am using Cyclone II and Quartus II.
View ArticleDE1 USB communication
Hello, I was wondering if there is any way to have USB communication on the DE1 board? I read a few articles regarding use of the Virtual JTAG which seemed interesting (I am yet to try those). The Qsys...
View ArticleError: License for encrypted file not available
Hi guys, I am relatively new to the Altera FPGA boards. I am using a Cyclone II board. I created a NIOS II system using qsys and I created a project in Quartus (version 13.0) as per the tutorials....
View Articlehow much current can EP2C5T144 drive to a load through its output pins???????
Your pdf files are so huge and filled with pedantic little details which I dont require, I cant even find the answer to this incredibly simple question and to be quite fair im very disappointed. This...
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