Hello,
I am trying to realize a VHDL code able to generate a complex baseband dual tone signal. What i would like to to is then send this signal through the HSMC port to a DAC evaluation board, where the DAC is reconstructing the analog signal.
I have started my design in this way, I basically use a PLL in order to generate the clock for two different NCO Megacore functions (configured to oscillate at two different frequencies with CORDIC implementation, and to send in output both sine and cosine signals).
After that I sum the two I components, and Q components together using a 16 bit adder block.
After this I have connected an IO_LVDS_BUFFER making the signal differential to connect it to the LVDS transmitter on the HSMC port, ready to be sent to the DAC.
Here I am completely leaving apart the fact that I should interleave the I and Q components, as the dac would like.........
Is there somewhere a nice example to start with, for the realization of a complex dual tone sinusoidal signal?
Greetings,
Giovanni
I am trying to realize a VHDL code able to generate a complex baseband dual tone signal. What i would like to to is then send this signal through the HSMC port to a DAC evaluation board, where the DAC is reconstructing the analog signal.
I have started my design in this way, I basically use a PLL in order to generate the clock for two different NCO Megacore functions (configured to oscillate at two different frequencies with CORDIC implementation, and to send in output both sine and cosine signals).
After that I sum the two I components, and Q components together using a 16 bit adder block.
After this I have connected an IO_LVDS_BUFFER making the signal differential to connect it to the LVDS transmitter on the HSMC port, ready to be sent to the DAC.
Here I am completely leaving apart the fact that I should interleave the I and Q components, as the dac would like.........
Is there somewhere a nice example to start with, for the realization of a complex dual tone sinusoidal signal?
Greetings,
Giovanni