How LEs are aligned

Hello

I have three questions considering about how LEs are aligned and placed.

(1)
I want to know how LEs are aligned "physically."
Because by the default of Quartus II LEs are sometimes placed far from the I/O elements which are intented to be used, I think the alignment you can see on Chip Planner is not real and real LE alignments should be something different.

(2)
As mentioned above, the default placement of LEs by Quartus II seems weird to me.
So I want to know the principal of the LE placement by Quartus II. There must be some logics about the placement (for there is no "randoms" in computer world).

(3)
I want to know where "unassigned" I/O elements are connected to.
In most ICs, I/O ports have fixed voltage (GND or Vcc) to avoid the through-current to the CMOS.
So what I am thinking is that the unassigned I/O elements must be connected to GND or Vcc.

Any replies are appriciated.

Thanks