Error 23031 when using the EDA Simulation Library Compiler within Quartus II...
I recently installed a fresh version of Quartus II 12.1 Web Edition on a Win7 Enterprise SP1 machine. When trying to compile the simulation libraries using the Quartus II 12.1 Web Edition EDA...
View Articlemonitoring all the pins
I'm working in a project that has been working before, there is one fpga emitting data and the other receiving, the transmitter I know that is working but the receiver is not working. Before the...
View ArticleFPGA Multiplication Resource Utilization
Hi, I need to do 18x7 multiplication and my FPGA doesnt have the built in DSP blocks, so I am using behavioral code in the source code to do the multiplication. It is taking around 190 LUT to do this...
View ArticleHow LEs are aligned
Hello I have three questions considering about how LEs are aligned and placed. (1) I want to know how LEs are aligned "physically." Because by the default of Quartus II LEs are sometimes placed far...
View ArticleDDR3 SDRAM HPC ip core, about OCT and RUP/RDN pins.
Hi all, I have a question in designing DDR3 ip core: - When designed DDR3 interface, I forgot to pull up and pull down RUP/RDN dedicated pins in DDR3 funtion banks. So, can I compile project with DDR3...
View ArticleVGA resolution problem
Hello all, I am using the University program media computer and this works. As I see how it is set up the VGA pixel buffer is 320x240 and then it's scaled to 640x480. But I want to have a native...
View ArticleHow do I satisfy design assistant rule D102? (Multiple data bits CDC)
I'm having a hard time satisfying Quartus II design assistant rule D102: "Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in...
View ArticleIs it possible to use Cyclone V SX HPS GPIO pins as FPGA GPIO pins?
As title describes: Is it possible to use Cyclone V SX HPS GPIO pins as FPGA GPIO pins? As example: I have some block of logic in VHDL. this logic communicates with some external integrated circuit....
View ArticleFIFO to SGDMA, FIFO Stays FULL memory not written.
Hello all, still a little new to NIOS and avalon components, but I've been going at it for a few days and I'm a bit stumped. I setup an external counter being fed through a custom Avalon component....
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Memory Mapped Master interface in Qsys lacks associated reset
I meet some problem when i using the qsys to complete a simple design.My design includes 3 component.The first one is custom_masters_hw.tcl downloaded from the website.The second one is generated by...
View Articlelvds outclock divide factor
Hi All, I have a specific question regarding the LVDS TX and LVDS Rx megafunction. I am sharing pll's between the tx and rx. I am trying to get the lvds outclock datrate and clock frequency to be the...
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DE0-nano's adxl345 accelerometer via SPI-3 wire
Hello, Recently I started a project in wich I have to get the datas from the 3 axis of the accelerometer ADXL345 of the DE0-nano board. I only have some skills in VHDL but i can understand verilog. So...
View ArticleProblems with the CVI and CVO Sof-Signals
Hi, I really need help. I have a simple VideoProcessing Modul. I hav a CVI --> ChromaResampler --> CVO, and a Cylone IV E I have different clocks for the PixelClock-Input an the PixelClock...
View Articlespecifying false paths
Hi All, I'm a bit confused on specifying false paths and the use of -to, -through, and -from. For -to and -from, do these have to be the source (q) and end (d) of some datapath? Or can they be...
View ArticleError when porting from SOPC Builder to QSys
Hi Recently porting an old design from SOPC BUilder 11.1 to QSys 12.1. I have the following QSys errors: Error: System.MeasureDVI: Could not determine TOP_LEVEL_HDL_MODULE because file...
View ArticleAcquiring data from files
I am trying to multiply a series of values that I am getting from txt files. My ideia is to get the data from 1 file, multiply for every data from the second file, get the second valor from the first...
View ArticleDoes Cyclone4 support DDR2 DIMM?
The Altera technical support told me that Cyclone 4 does not support any DIMM, but I cannot find any official statement about that. If I implement the DDR2 DIMM using Cyclone4, what is the point I...
View ArticleUsing PFL megafunction to configure 7 stratix V FPGAs using two 2Gb CFI Flash
Hi, In our project we are using 7 Stratix V FPGA on our board and we are using MAXII CPLD as configuration controller for configuring these FPGAs in chain. We are using Altera pfl mega-function inside...
View Articlecyclon II
hi ... i just started learing FPGA and i started from cyclon II chip .its core voltage is 1.2v and vcc 3.3v . can i directly apply 3.3v to any I/O pin? there are some dedcated clock pin. i have to...
View Articlesampling frequency
hi ... there is fpga based logic analyzer at sump.org/projects/analyzer/ it is implemented on spartan 3. i was reading and trying to understand how it is coded. its sampling frequency is 100MHz at...
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