Hello all, still a little new to NIOS and avalon components, but I've been going at it for a few days and I'm a bit stumped.
I setup an external counter being fed through a custom Avalon component. This is then fed into a FIFO I setup in qsys. This works OKAY and it fills up the FIFO just fine. This is a non-packet FIFO so it's then fed into a bytes_to_packet converter (many little timing adapters and data format adapters are added auto-magically by qsys as well). This eventually makes its way to a SGDMA which is linked to onboard memory so that I can view it through the in system memory viewer.
So my problem is as follows, I can feed the data into the FIFO and I signal tap the output of the FIFO and can see the data coming out for a very short time. The FIFO becomes exerts a high FULL signal and all transmission stops. I'm not sure why the DMA isn't reading data off the FIFO (or if it needs something else to do that) to keep it empty and more importantly, even though it reads a small amount of data NONE of it makes it to that onboard memory block that I can see (after firing up NIOS and setting up my descriptors as per the SGDMA example design). I attached my QSYS build and was hoping for some insight, thanks.
i.imgur.com/4Yw7D.png
Upon looking at this further, my ready_in isn't being asserted at the DMA. I'm setting the registers correctly, I've got two descriptors with the control byte of the last one set to 0 so that it's not owned by hardware. I'm guessing the DMA SHOULD be starting because I run
Inside the function it points the controller to the descriptor and then sets the run bit in the control register via:
I setup an external counter being fed through a custom Avalon component. This is then fed into a FIFO I setup in qsys. This works OKAY and it fills up the FIFO just fine. This is a non-packet FIFO so it's then fed into a bytes_to_packet converter (many little timing adapters and data format adapters are added auto-magically by qsys as well). This eventually makes its way to a SGDMA which is linked to onboard memory so that I can view it through the in system memory viewer.
So my problem is as follows, I can feed the data into the FIFO and I signal tap the output of the FIFO and can see the data coming out for a very short time. The FIFO becomes exerts a high FULL signal and all transmission stops. I'm not sure why the DMA isn't reading data off the FIFO (or if it needs something else to do that) to keep it empty and more importantly, even though it reads a small amount of data NONE of it makes it to that onboard memory block that I can see (after firing up NIOS and setting up my descriptors as per the SGDMA example design). I attached my QSYS build and was hoping for some insight, thanks.
i.imgur.com/4Yw7D.png
Upon looking at this further, my ready_in isn't being asserted at the DMA. I'm setting the registers correctly, I've got two descriptors with the control byte of the last one set to 0 so that it's not owned by hardware. I'm guessing the DMA SHOULD be starting because I run
Code:
alt_avalon_sgdma_do_async_transfer(DEVICE, &dma_descriptors[0])Code:
control = IORD_ALTERA_AVALON_SGDMA_CONTROL(dev->base);
control |= (dev->chain_control |
ALTERA_AVALON_SGDMA_CONTROL_RUN_MSK |
ALTERA_AVALON_SGDMA_CONTROL_STOP_DMA_ER_MSK );
IOWR_ALTERA_AVALON_SGDMA_CONTROL(dev->base, control);