Basic work flow question on Altera DSP Builder
Hello all, OK so far I have created a model in Simulink then after that was working I implemented the same model using Altera DSP Builder Advanced Blockset. I followed the Design Guidelines and used a...
View ArticleConvert project from Quartus 2 to Max+plus
Hello everybody !!! I'm new user program Quartus. I have question about program Quartus 2. Is it possible convert project from Quartus 2 to Max+plus? It's very important to me. Thank you in advance for...
View ArticleProblem opening .qar archive
I have created a .qar file from a working project in 11.1, which contains an SOPC Builder project. Re-opening the .qar file in 11.1 Quartus seems OK, but whenever I try to run QSys or SOPC Builder from...
View ArticleCritical Warning: Timing requirements for slow timing model timing analysis...
Hello, I am implementing a design in Quartus 2. The compilation gives me:Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. I have...
View ArticleStratix V Transceiver Architecture
Has anyone successfully implemented 4 independent 10G Low Latency PHY transceivers with 4 separate refclks? I know it can be done with two independent PHYs by assigning one on the left and the other...
View ArticleProper method pulling header files into the Software Build Tools *_sw.tcl
With the legacy tools, header files seemed to get pulled over correctly as long as the directories were properly specified in the SOPC builder. I'm running into some difficulties getting header files...
View ArticleGlitch free operation post-mux between two asynchronous clock domains
I have two single-bit signals running in separate clock domains (~39MHz and ~270MHz). Each can be assumed to be arriving from registers. I need to mux these two signals depending on a flag and output...
View ArticleSome basic workflow questions
I am trying to understand the command line tools and I was hoping someone could help me out with the design flow. I'm used to Xilinx tools and just started learning Altera. What I gather from...
View ArticleQDRII+ IP core error
Hi all: I am using QDR II + IP core of ALTERA, but the IP can't work correctly. I test the core in my customized board with quartus II 12.0 SP2(windows XP sp3) and find some results: 1. The device in...
View ArticleQDR II + IP core error
Hi all: I am using QDR II + IP core of ALTERA, but the IP can't work correctly. I test the core in my customized board with quartus II 12.0 SP2(windows XP sp3) and find some results: 1. The device in...
View ArticleLooking For ASIC/FPGA Developer SHA256
I am looking for information on where to locate a developer to create a fpga or asic to process sha256 transactions. Please reply here for now, still new to the forum so I cannot PM. Or email me at...
View ArticleHow could I use DMA IPcore to transfer data continuous
Hi Everyone: When I use the dma ipcore to transfer data,I found a question"How could I use DMA IPcore to transfer data continuous",for example,when one dma transfer finished,how to trige another dma...
View Articlehow to connect analog input directly to FPGA Altera board?
hi; I want to implement Sigma Delta ADC on Altera DE1, i wrote the code and run on QuartusII; now i want to know is it possible to connect the analog input directly to the board? as in my code the...
View Article"system id mismatch" error for multiprocessor application
Hello everyone, I am trying to implement a microprocessor application by using two NIOS II. However, I have got a "system id mismatch" error during the debugging process. This error occurs for the cpu2...
View Articlekernel_execve locks
Hello all, I am trying to port a working linux under development board to a board designed with similar features. I use uboot, Linux 3.2.0-rc5 and jffs2 root filesystem (all these working on dev...
View ArticleSoftware / BSP Building with ARM Soc/Linux OS
I have been learning the development flow using altera tools the last few weeks. So far I understand how to design NIOSII based hardware using Qsys, add FPGA connections using Quartus, then build the...
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RLDRAM II Simulation Issues
I generated a RLDRAM II controller in Quartus and now I'm verify the functionality. The status of the RLDRAM controller passed (local_init_done and local_int_success), but the mem_we_n appears 27.5 ns...
View ArticleBemicro SDK, where or how to buy?
Hi, I would like to buy a Bemicro SDK. I have tried to buy it in arrownac.com (US site) but it was not possible. I had several problems trying to order and finally, when I could order, 1 week later...
View ArticleReceiver to FPGA
Hi, My project goal is to connect a receiver of 15Mbps to computer through FPGA DE3/DE4. I want to ask which component should i connect my receiver? and if i need clk from the receiver as well? Tnx Tzahi
View ArticleCan't launch modelsim starter edition ubuntu 12.04
Hi there, I have just installed altera modelsim starter edition on my ubuntu 12.04.1 64-bit laptop. I downloaded the installer, run it with the root user. I selected an installation folder (not the...
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