ELF ,bin file
I am working with Altera DE1 board and i am trying to build a system based on NIOS 2 .. my system design is successfully loaded through quartus programmer now i want my nios 2 program to be loaded to...
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Unable to mount root fs on unknown-block(0,0)
Hi everyone, could anyone answer my question ? Thanks! 1.I got it by using 'default all setting(lose changes)' without chooing the MTD now! Code: Linux version 3.5.0-rc4+ (root@localhost.localdomain)...
View ArticleCan Qsys implement two processor with sharing 2 ddr2 sdram?
the scheme is : on Stratix IV EP4SGX230 {Processor1 Processor 2} |/ _________ \| {ddr2SDRAM1 ddr2SDRAM2 } operations: 1,time1 ,Processor 1 ACESS SDRAM1,Processor 2 ACESS ddr2SDRAM2 2,time2 ,Processor 1...
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DAC5672 Sine output
Hi All, I am trying to generate a simple Sine wave from DAC5672 on my Hsmc daughter card from Terasic . The NCO i am using is from Open Cores , i works fine in simulation as shown in screen shot...
View ArticleStratix Hardware design
hi guys, i am using Stratix V device for our new design, i have a problem when doing the power estimated, we want used two type of GX lane, one is 2.5G SerDes and the other is PCIE GEN3 hard IP. we i...
View ArticleCompile the AppWeb Webserver
Hey, i'm actually trying to compile and run the AppWeb Webserver with the uClinux distribution and the ArriaGX II Dev Kit. I followed some Guides in the Altera Wiki to compile the uClinux and...
View ArticleDDR3 with HPC/Uniphy cores: what is the reason of the delays?
Hello. I am trying to work with DDR3 on Stratix V. I've made a variation of DDR3 controller (HPC/Uniphy) and try to write there an information. When I choose the "Half rate" for the logic/DDR3...
View ArticleCholesky algorithm IP
Hello, We're trying to use DSP Builder Cholesky algorithm (currntly we're simulating using ModelSim the Cholesky with your TB). In the entity there are 2 undocumented inputs: InUpper_s, ProcUpper_s....
View ArticleWin7-Problem with NIOS-II debugger, can't start gdbserver
I have the following problem: I'm running the (32bit) Quartus 11.0sp1 and Eclipse built tools for the NIOS-II on a Win7-machine with 64bit. An additional standalone-programmer for Quartus 12.0sp2...
View ArticleQuartus 12.1 crashing alot
Has anybody else experienced many, many crashes with the new release? I have had about a dozen at least in the last few days(3 just today). All last year I probably had 5 between 11.0 through 12.0 SP2....
View ArticleTiming constraints, collection naming, tool flow, and clock gating
Hi All and sorry for the verbose subject. I'm trying to close timing on a design which uses a lot of clock gating throughout the design. I believe the mapper does not read in a specified SDC file, but...
View ArticleMaximum Transform length for Startix IV FFT IP
Hi, I used Altera FFT IP to design my project. The quartus version is 9.0 while IP version is V9.0 Build 132. I tried to configure transform length to 32768 but I found maximum Transform length is...
View ArticleHow to use Engineering Change Management with the Chip Planner (ECO)
I have a question on how to use this ECO feature for long term. I started to use this ECO feature and I like the quick refit time. So I moved some LE in a LAB to a different location. Its real easy to...
View ArticleStoring values as non-volatile in SRAM during RUNTIME
:confused: I am working on a meter based on Cyclone III (using all logic on Quartus and display related using NIOS). I now want to store/change some value during run-time and recollect on consequent...
View ArticleDo VHDL project example in altera support for DE2-115 Development Board?
Do VHDL project example in altera support for DE2-115 Development Board? i bought DE2, would like to try ethernet function, then i found example in altera site, but it said for NIOS 2, can it run in...
View Articlecompiler error in application
Hi everyone, I create a new NIOS II Application and BSP from Template Hello MicroC/OS-II (NIOS 12.0 SP2 system). I add the altera_iniche software packages in the BSP editor and checked in the make...
View Articlecompiler error in application
Hi everyone, I create a new NIOS II Application and BSP from Template Hello MicroC/OS-II (NIOS 12.0 SP2 system). I add the altera_iniche software packages in the BSP editor and checked in the make...
View ArticleNIOS II self test
Hallo together. Does somebody know if there are any special rudiments for a NIOS II (C4) to implement self test functions? Is there any documents from Altera, how to implement such testing functions?...
View ArticleHow to pin list..?
Hi I am beginner in VHDL. I made a code and it's working very well. when I entered the 'Pin planner', there is no pin list. How can I see pin list? I have to assign the pin!! Thanks for reading
View ArticleVIP Suite Scaler II Megacore function
Hi Alterians, My design consists of a Test patter generator followed by a Scaler ii followed by a clocked video output. My aim is to scale down the input resolution (1280*720) to a standard VGA...
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