Using Packed Registers in Stratix V ALM

I dont seem to be able to get Quartus to use the extra Registers available in the Stratix V ALM, this would help a great deal in my pipelined design.
Am I missing a special option or setting?

This simple program is an XOR gate followed by two registers, and it looks like Stratix V should be able to use the two output registers to implement this
by feeding the output of the first register back round into the datae/dataf inputs.
(The first register only feeds the second, and both have the same reset, clock).

When I assign this to a LogicLock region of 1 LAB I get "LogicLock region is too small to contain its members".

Attached Files

• testmuxregpack.vhd (749 Bytes)