PCIe + DMA project on DB4CGX15
Hi all, I'm new in PCIe developing and want your help. I'm using DB4CGX15 evaluation board from DevBoards. I need to transfer data from outside to PC. The data is 32 bits width and clock is 85 MHz....
View Article10_100_1000 Mbps tri-mode ethernet MAC
Hi, I want to implement gigabit Ethernet port with Altera DE2-115 board having Marvell Phy(88E1111). An alterantive is to use IP core but its not free. I saw in opencore.org there is "10_100_1000 Mbps...
View ArticleQuartus 13 and University Program Vector Wave File problem
Hello, I have installed Quartus II 13, ModelSim-Altera and the University Program. I created a simple logic structure in a Block Diagram, compiled (Processing | Start Compilation), set ModelSim-Altera...
View Articlehow to simulate (modelsim altera version) alt4gxb
I'm banging my head on the wall trying to figure out how to simulate a stratix iv gx transceiver, alt4gxb. I'm getting a slew of the following types of errors: # Region:...
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Using Packed Registers in Stratix V ALM
I dont seem to be able to get Quartus to use the extra Registers available in the Stratix V ALM, this would help a great deal in my pipelined design. Am I missing a special option or setting? This...
View ArticleConditional when statement with port map
Hi, I am trying to write a conditional concurrent port map without success. Here it is. Code:  map_gen: for i in 0 to N-1 generate           map_0: entity work.my_tff(arch) port map('1',...
View Articleget value from master_read_32
Hello evryone, I am trying to do a GUI interface with tcl to load the .sof that I generated into the FPGA with tcl. I want also in this tcl script read from a memory adress, get a value and put it into...
View Articlesynthesis
hi all i have sinus and cosinus synthesible code, the area of synthes is important for me, can eyeveryone help me? thanks
View ArticleBug in Quartus 13 and Waveform Simulation
Hi, in Quartus II 13 when trying to run a RTL functional simulation (eg. from the Simulation Waveform Editor Editor) nothing happens. I think the setup is right (the design is in VHDL, compiled...
View ArticleModelSim - "Create Pattern Wizard" Missing in New Version (10.1d)? [SOLVED]
I just upgraded from ModelSim-ASE 10.0c to 10.1d, and I found that the nice "Create Pattern Wizard" feature has disappeared. Usually, I would activate this feature by right-clicking on a Net in the...
View ArticleDefault run time won't stop increasing
Hi there, I'm currently running Quartus II Version 13.0 sp1. While using the ModelSim-Altera to simulate waveforms I wanted to change the Default run time in Simulate->Runtime options to 20 ns,...
View ArticleMAX V IEEE 1532 BSDL Files
Hello everyone, I am working on a university project on which I try to figure out how to program a MAX V CPLD via the IEEE 1532 standard. The according datasheet reads, that there are IEEE 1532-BDSL...
View ArticleReference Design, What should I do with DNI component??
I trying to design a board using the reference design of ALTERA cyclone V, I found many DNI components (resistors and capacitor), what i have to do with this components?, opened circuit? In the LPDDR2...
View ArticleCyclone II Device FIles Missing - Where did they go?
I started a project yesterday, using the cyclone II device on the ED1 board I have. I open Quartus II today and open the project and is says I need to select a new device since the cyclone II device I...
View ArticleRegister to remember Compiling day or time, version control
Hi Currently, I am try to do version control. I am wondering, is it have anyway to record when I did this compiling? TINGMING
View ArticleQsys-script FAILED
Hi all, Finally moved to sdk ver 13 but bumped into another issue. aoc fails with the following message: ... Error: Qsys-script FAILED See all.log for details. all.log shows the following (single)...
View ArticleStrange interference on THDB-ADA HSMC connected to DE2-115
I'm getting a strange problem when using the DAC on a project running on the DE2-115 and THDB-ADA (hsmc). When I program the board, at first, everything is fine and the waveforms coming from the DAC...
View ArticleSystem Console Memory Reading
Hi, everyone. Today I try to use system console to communicate with DE2-70 FPGA board. I want to know what happens when the specified memory address exceeds the reasonable range. For example, Code: set...
View ArticleSimple PCIe DMA
I guess I could try to find the appropriate documentation, but I'll cheat and ask here! I need to find which DMA block to ask our HW team to add to qsys in order to do burst PCIe transfers from fpga...
View ArticleCyclone V SoC AHB BUS
Hi I need an AHB bus outside the hps with qsys. The HPS has an h2f_axi_master and f2h_axi_slave_bridge. The qsys interconnect guide is not helpful :cry:.. some idea where to start? some examples? or...
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