Access On-Chip memory from NIOS and custom logic
Hello everyone. I am working on an embedded control system running on a Cyclone IV FPGA. The control algorithm (custom FPGA logic) reads values (16 bit integers) from a pre-computed (offline)...
View Articlearchive or revision control for Eclipise project
I am working on a project with two other enginees. We are all in very different locations and have been using Subversion revision control to keep our design files in sync. This has worked OK for all...
View ArticleGigabit Transceiver Lane Assignement_5SGXA7KF35
I am using StratixV 5SGXA7KF35 for a Prototype design. In this design, x8 Gigabit Transceivers are used for FPGA to FPGA interconnection. Protocol is not yet defined. It may be any one of the following...
View ArticleDEO_Nano as onboard system
Hi Guys, I am still beginner in FPGA. May i ask some suggestions? Now, i am doing project with DEO_Nano ALTERA Cyclone IV. I use QUARTUS II 10.1 and NIOS II. I want to make my system as onboard system....
View ArticleLicensing Question
I ordered a license file for my quartus software. When i want to download the license file, is it important to download the license file with the development computer? My development computer has no...
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Quartus II, Power analysis problem
Dear friends, I have encountered a problem using power analysis tool. I have, manually, created a .VCD file by ModelSim. When i run the Powerplay power analyzer tool, i got the result 0.00 mW for a...
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niosII debug error
i have this problem several days.After build the project,i debug as Local c/c++ application, but error appear报错.jpg ,i do not know how to solve.Anyone knows?3Q:):):) Attached Images 报错.jpg (90.5 KB)
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Primitive
So i am currently converting some of our companies work done on Xilinx FPGA to a Altera FPGA. I have been working on it for a few mounth so far with litlle to no problem. But All i really had to do is...
View ArticleQsys IP component for Fuzzy Filters (FIRE)
I need to use Fuzzy Filters (FIRE) to correct noise on video frames or images. Do I need to implement it or is there any IP for Qsys plug and play? thanks,
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DE1 GPIO 5V tolerance
Hello to all, in the DE1 board GPIO outputs are protected only with a resistance of 47 ohms. To make it compatible with the 5V inputs and outputs are just two diodes toward the positive and the other...
View ArticleComment block in ModelSim?
Hi Is there a way to comment out a section in a .do file in modelsim? I can comment out a line using "#" but was wondering what is the syntax for commenting out a section (/*........ */ in C) Thanks
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DDR memory access problem
Hi all, I am a new guy to NIOS world, recently I am working on a project to catch 100MHz ADC data and store it in DDR memory, I use SOPC to build NIOS-II CPU and related slaves such as system_id, epcs,...
View Articleerror 176310 on dual-purpose pins
I am getting the error- Can't place multiple pins assigned to pin location Pin_12 while compiling a Cyclone IV device. I am hoping to use the DCLK IO as an application pin and have set...
View ArticleUART stops working when interrupts are enabled
Hi all, I have used the NIOS II environment for several years, but am at a loss at the following problem: The UART stops working (no more output) when I enable UART RX interrupts. I have tested it with...
View Articleuse tse mac loopback
i want to use the loopback function of tse mac. how could i start it? thank you in advance! FangQJ
View Articlewhy miss EP4SGX70HF35/EP4SGX110HF35 in stratix iv handbook?
in stratix iv handbokk ,http://www.altera.com/literature/lit-stratix-iv.jsp I find few information about EP4SGX70HF35/EP4SGX110HF35? no update or I miss sth? thx!
View ArticleCyclone V Transceiver Reference Clock for SATA
I have configured a Cyclone V transceiver for a SATA development and have a very basic architecture running on the Cyclone V GX development board in a loopback fashion. The transceiver is configured...
View ArticleWhy does quartus think my signal is a clock?
Here is the code snipped Code: begin write_register <= '1' when ((chipselect = '1') and (write = '1') and (byteenable = "1111") ) else '0'; process (clk,reset_n) begin -- process if...
View ArticleMAX II Programmable Register
Hi All, I'm working with a MAX II EPM1270. In the MAX II documentation the register inside each logic element (LE) is referred to as programmable, capable of D, T, JK, or SR operation. What's meant by...
View ArticleComplex Coefficients with FIR Compiler II
Is it possible to use complex coefficients with the FIR Compiler II? If so, what notation is used to specify this when loading coefficients from a file into the wizard? I've tried i and j, but the...
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