Hello everyone.
I am working on an embedded control system running on a Cyclone IV FPGA. The control algorithm (custom FPGA logic) reads values (16 bit integers) from a pre-computed (offline) Look-Up-Table.
A new data sample will only be needed every 1/10 of a millisecond (Ts = 1e-4 s)
I decided to utilize the on-chip memory (M9k) blocks since a.) this offers the lowest latency and b.) the size of the memory should be sufficient.
The system should do the following:
- At power-up read data from flash and store it to the on-board memory
- Allow custom FPGA logic to read this data (no write only read)
What would be the best way to implement this? I would incorporate the flash storage in QSYS and then write a C-program for the NIOS II processor to facilitate the task of filling the On-Chip memory at start-up. The on-chip memory should be configured in dual-port mode.
From here I have some questions...
Is it possible to simultaneously access the on-chip memory in my custom logic through megafunctions?
Would it be better to use a custom QSYS component and access the memory via the Avalon-MM interface and afterwards provide the data to the outside FPGA logic via Avalon-Conduit interface?
Is there something fundamentally wrong with this approach?
I would really appreciate your expertise.
I am working on an embedded control system running on a Cyclone IV FPGA. The control algorithm (custom FPGA logic) reads values (16 bit integers) from a pre-computed (offline) Look-Up-Table.
A new data sample will only be needed every 1/10 of a millisecond (Ts = 1e-4 s)
I decided to utilize the on-chip memory (M9k) blocks since a.) this offers the lowest latency and b.) the size of the memory should be sufficient.
The system should do the following:
- At power-up read data from flash and store it to the on-board memory
- Allow custom FPGA logic to read this data (no write only read)
What would be the best way to implement this? I would incorporate the flash storage in QSYS and then write a C-program for the NIOS II processor to facilitate the task of filling the On-Chip memory at start-up. The on-chip memory should be configured in dual-port mode.
From here I have some questions...
Is it possible to simultaneously access the on-chip memory in my custom logic through megafunctions?
Would it be better to use a custom QSYS component and access the memory via the Avalon-MM interface and afterwards provide the data to the outside FPGA logic via Avalon-Conduit interface?
Is there something fundamentally wrong with this approach?
I would really appreciate your expertise.