Set_input_delay misunderstanding

Hello:

new to sdc constrains


I have 2 cases to constrain my serial data coming in and trying to understand the differences
Case 1 has been done in previous projects right or wrong but shows no timing violation. In my project I am getting a small negative slack for hold time (on Fast timing)

Case 2 shows no timing violation (positive slack)
This case was created based on reading the Timequest user guide. However, I don't understand how RX_CLK relates to the virtual clock


It seems that the total tCo in one case should be different to the other on default relationships??

Which one is correct? For me, case 1 ties directly to the clock input on the FPGA and the tCo should account for board delays , margin and the spec tCo of the device.


FPGA input is
RX_CLK -Pin
RC_Data0- pin

tComin and tComax are defined

RC_Data0 should be clocked into a shift register in the RX_CLK clock domain

Case 1
create_clock -period 20 [get_ports { RX_CLK }]
set_input_delay -clock { RX_CLK } -clock_fall -min -$uC_tCOmin [get_ports { RC_Data0 }]
set_input_delay -clock { RX_CLK } -clock_fall -max $uC_tCOmax [get_ports { RC_Data0 }]




Case 2
create_clock -period 20 [get_ports { RX_CLK }]
create_clock –name RX_CLK _Virtual -period 20

set_input_delay -clock { RX_CLK _Virtual } -clock_fall -min -$uC_tCOmin [get_ports { RC_Data0 }]
set_input_delay -clock { RX_CLK _Virtual } -clock_fall -max $uC_tCOmax [get_ports { RC_Data0 }]

thank you