Hi,
Please consider the following code:
Regarding the line "report", I can´t synthesize this code. It is produced an error.
Everything like report "message 1" & "message 2" (considering messages 1 and 2 only text messages) it synthesizes well and produces me the desired note message.
If I try report "message" & xxxx, where xxxx is N, a'length, or any value different than a simple text, it produces an error.
Error (10327): VHDL error at mux.vhd(18): can't determine definition of operator ""&"" -- found 0 possible definitions
How can I see my desired message?
Regards
Jaraqui
Please consider the following code:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_package.all;
entity my_mux is
generic(N: integer := 8);
port(x: in std_logic_vector(N-1 downto 0);
a: in std_logic_vector(ceil_log2(N)-1 downto 0);
y: out std_logic);
end my_mux;
architecture arch of my_mux is
begin
aviso: assert false
report "size of a is " & a'length
severity note;
gen: for i in 0 to N-1 generate
y <= x(i) when (a = std_logic_vector(to_unsigned(i, ceil_log2(N))) and (i < (N-1))) else
'Z';
end generate;
end arch;Everything like report "message 1" & "message 2" (considering messages 1 and 2 only text messages) it synthesizes well and produces me the desired note message.
If I try report "message" & xxxx, where xxxx is N, a'length, or any value different than a simple text, it produces an error.
Error (10327): VHDL error at mux.vhd(18): can't determine definition of operator ""&"" -- found 0 possible definitions
How can I see my desired message?
Regards
Jaraqui