I have a Cyclone IV device as a managment device for the balance of circuitry on a board. The FPGA comes up prior to much of the rest of the board being powered. The FPGA will be responsible for sequencing the power up of various other power rails for other devices on the board. The majority of the FPGA's I/O will need to run at 3.3V
The FPGA must also communicate with other devices once they come alive, devices that operate at 1.8V.
To negate the need for dedicated 1.8V power supplies for the FPGA I would like to use the same 1.8V PSU that powers the other devices - a power supply that the FPGA is responsible for switching on.
So, one (or more) banks of the FPGA would remain off until that same FPGA switches the rail on, powering the other circuitry and its own I/O bank. This would typically be within a second of the 3.3V rail coming up, but could conceivably be (in a fault condition) considerably longer - or never.
Providing I power the appropriate I/O banks required for configuration immediately, can I sequence other banks at such intervals? Can I rely on the device booting?
The handbook tells me the POR circuitry monitors VCCINT, VCCA and 'the VCCIO level of I/O banks that contain configuration pins'. For that reason, can I assume an FPGA, connected as I intend, will boot?
The FPGA must also communicate with other devices once they come alive, devices that operate at 1.8V.
To negate the need for dedicated 1.8V power supplies for the FPGA I would like to use the same 1.8V PSU that powers the other devices - a power supply that the FPGA is responsible for switching on.
So, one (or more) banks of the FPGA would remain off until that same FPGA switches the rail on, powering the other circuitry and its own I/O bank. This would typically be within a second of the 3.3V rail coming up, but could conceivably be (in a fault condition) considerably longer - or never.
Providing I power the appropriate I/O banks required for configuration immediately, can I sequence other banks at such intervals? Can I rely on the device booting?
The handbook tells me the POR circuitry monitors VCCINT, VCCA and 'the VCCIO level of I/O banks that contain configuration pins'. For that reason, can I assume an FPGA, connected as I intend, will boot?