Multiply-by-2 clock
Hello, My design needs 2 clocks. One is the external clock and the other is the internal clock. The internal clock frequency = 2 x external clock frequency. The port names in my module are base_clock...
View ArticleProblem with Pin assignment Cyclone V Quartus v13.1 - Critical Warning (169244):
Have this error occurring Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank 3A have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or...
View Articledevice tree method + linux 2.6
Hi all, I want to have uclinux on my altera dev board specifically the device tree(dts) method of specifying the hardware and running linux kernel version 2.6.30 or less. I downloaded nios2-linux and...
View ArticleCyclone IV IO bank power sequencing
I have a Cyclone IV device as a managment device for the balance of circuitry on a board. The FPGA comes up prior to much of the rest of the board being powered. The FPGA will be responsible for...
View ArticleVHDL testbanch
Hi, I described clock divider from 50MHz to 1Hz. I also wrote testbanch, unfortunately it takes too much time to run 1 cycle at 1Hz. How can I make the simulation faster? Thanks
View ArticleIs there a performance difference between variables vs direct assignments
Several years ago I wrote a small (I thought) 8-bit micro-controller core called the Open8. The current model is based very closely on the old Arc-lite/V8 instruction set, though I've modified a few...
View ArticleHow to assign Name, Group etc module properties when you do "Export System as...
I am trying to create a subsystem in Qsys by using the "Export system as hw.tcl Component" command. When you do this it generates a useful hw.tcl file but its sets the module properties to default...
View Articlefloating-point computation capability
Hi there, I've read the OpenCL v1.0 specification and Altera's OpenCL programming guide. I just want to make it clear that: Altera OpenCL supports for single precision floating point computation in...
View ArticleEPM3128A Fitter Error after assigning a single pin
I am attempting to add 4 pins and a small amount of logic to an already existing design in my EPM3128A. I can successfully build under the following conditions: - Just the input pins (no assignments),...
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Can't open .qar file
Hello, The design example provided by Altera in the link: http://www.altera.com/support/exampl...ted-clock.html do not open. It gives the following error message : Error (20005): A license file is...
View ArticleQuartus compilation
Hi all, I am compiling the project using quartusII (altera 13sp1). Some time after compilation, when I load fpga with .sof file fpga doesn't provide me any output. If I compare the size of files for...
View ArticleReturn Codes
How to use return codes when programming the device by using the following command (included in the tcl-script): quartus_pgm --mode=as --cable=USB-Blaster --operation=pv\;file_name.pof Quartus II...
View Articlehow to add NOP in nios?
I'm trying to migrate a program in dsp to nios, and I wonder how can I implement the NOP instruction by HAL or ucosii?
View ArticleGetting data from a rtc device through I2C
Hi all, I would like to retrieve information from a RTC device which is directly connected to a GPIO, using the i2c protocol. So, the first step was to load the i2c-gpio driver with this piece of code:...
View ArticleChip new project
I have to make a new project, for three DC motors, incorporating the fuzzy logic control, which chip do you recommend? I have see the Cyclone 2, I sing it's OK.Thanks in advance regards Maurizio
View ArticleS4GX530 dev kit; HDMI audio not working
Hi All, I am using the AD9889B chip on the Startix 4 GX 530 dev kit. I am trying to get the audio up and running but unfortunately without any success. Setup: I have a 480p video test pattern output...
View ArticleConvert Dot Multiply from C2H to ???
I have the following simple vector dot multiply as a C2H accelerator. For some situations (but not all) regular NIOS running 50MHz on a 2C8 is fast enough running in code. I want to implement this as...
View ArticleProblem with Pixel Buffer DMA Controller back buffer
Hi I have successfully instantiate the Pixel Buffer DMA Controller university program IP core in QSYS and i was able to display the .BMP file on the screen but the problem is when i'm writing to the...
View ArticleMultiple Avalon-MM Master connected to DDR2 SDRAM Controller
My Design: I made my design on Qsys. I have multiple components with (Avalon-MM Master) connected to the same (Avalon-MM Slave) of DDR2 SDRAM Controller with UniPHY . My components are: * 3 Frame...
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