Multiple Avalon-MM Master connected to DDR2 SDRAM Controller
My Design: I made my design on Qsys. I have multiple components with (Avalon-MM Master) connected to the same (Avalon-MM Slave) of DDR2 SDRAM Controller with UniPHY . My components are: * 3 Frame...
View ArticleDe2-115
I have DE2-115 development kit . I want to use it for USB data read /write with the FPGA onboard from PC using labview. 1.how to interface FPGA with USB vhdl code ? any example available? 2.how to...
View Articleuse of cordic rotation method to implement FFT in VHDL
Hi,I have implemented radix2/4 & split radix FFT algorithm without using cordic.They are running fine...o/p is coming but the problem is that the code is non synthesizable.To make that code...
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Single wire can bus and bidirectional pin coding
Hi all, I am a beginner, trying to implement a One-wire CAN bus coupler logic on a Cyclone IV FPGA. The FPGA communicates to a disconnectable external slave device via a pin using CAN bus. The pin can...
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JTAG TCK droop using USB Blaster(Ver B) and Cyclone II
I have a NIOS-II processor in a Cyclone II which I am trying to debug using a USB Blaster (Ver B.) cable and The NIOS-II eclipse tools. However, the JTAG communications are highly unreliable. VCCIO and...
View ArticleNIOS BSP custom Instruction Flags
Hi, I am using NIOS IDE V 8.1 with SOPC and currently I am using the following source: (http://www.alterawiki.com/wiki/Custo...ing_Point_Unit ) for setting the custom instruction for setting up the...
View ArticleInstalling quartus II on Debian Wheezy(7.1)
I've been working at installing Quartus II on Debian Wheezy(7.1) and have been following the following guide, which was written over a year and a half ago:...
View ArticleTrouble running the DE2-115 system CD. Control Panel displays error
I'm running the lastest v13 Quartus II on windows 8 from paralles on my macbook pro. Software installed successfully. I performed the power-on test and everything is working correctly. I inserted the...
View ArticleHow to sdream read UFM's data use the default interface
Hi Guys I use a EPM240T100C5 CPLD for our design. I hope to stream read UFM's data don't use interface protocol. I can erase/program and read UFM. Now, I hope to stream read UFM's data via CPLD. I...
View Articlefdisk then mkdosfs on non-mmu system
Thanks in advance. I'm using the Cyclone II Evaluation board that has the Compact Flash adapter. I can put in a compact flash that is 32 GBytes and I have no problems using all 32 GBytes of the Flash....
View Articleremoval of uClinux-dist and u-boot gits from sopc server
Dear all, As our network bandwidth is limited, we have to remove some git repo which are either deprecated or unnecessary. The uClinux-dist, which was cloned from Blackfin uclinux, was deprecated since...
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USB Blaster Driver Software cannot install on Windows 8. Help!?
I'm running Windows 8 in parallels with OS 10.8 on a mac. It has been a miserable "Windows 8" adventure so far. I have downloaded and installed Quartus II v13 SP1. It has installed successfully or so...
View ArticleDSP Development Kit, Stratix III Edition vs. Stratix III FPGA Development Kit
Dear all, Can anyone tell me what is the main difference between DSP Development Kit, Stratix III Edition (http://www.altera.com/products/devki...t-st3-dsp.html) with Stratix III FPGA Development Kit...
View ArticleGet non dedicated input routed to a PLL?
I have a Stratix III design which literally just routes an input clock to an output pin (it's a very expensive pieve of wire). The clock was just to be used for time-stamping so the quality was not a...
View ArticleNios SPI Master and interrupt from slave
Hello forum !! I have another issue i can't solve.. I have a nios2 processor running and I use a SPI protocol (in which I am the master) to communicate with a slave hardware. The slave, under several...
View ArticleGlobal Variables and debugging
I am using a system with a NIOS II/f and a level III debugger. I am writing a simple (C) program and I am running the code and data from 32K bytes on on chip ram for testing purposes. The program...
View ArticleRegarding selection of appropriate board for application development
I would like to have suggestion from Altera users regarding the most appropriate board to select for my task of DSP and real time image processing development application. I have been suggested with...
View ArticleEnable VGA on DE2-115
Hi everyone I have successfully port uClinux on DE2-115 and now I want to use the on board VGA There is a frame buffer on the uClinux wiki page but somehow the frame buffer core is not available Is...
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Simplest way to transfer N video frames from Cyclone III Dev Kit to host PC?
Hi, I am working on a video design using Cyclone III Development Kit. I have got the streaming video pipeline working. Now, I need to tap this avalon-ST video path and transfer say 50 video frames the...
View Articlesmart parking
i need to design a car park indicator system for a space with 8 lots. With two gates each entrance to the parking lot And one exit from the parking lot. Hardware works on the principle of LDR Once the...
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