ModelSim simulation result is different to run in real FPGA

We use an EP1C6T144 chip as an SPI master to receive data from ADCs. The FPGA state machine is successful and receives data correctly in ModelSim simulation, but always shorts 1 bit shift if run on real FPGA chiip. The simulated waves and timing are exactly same to ADCs specification and also same to we observed real signals in scope. We are able to narrow down the problem to a paragraph of VHDL code:

----
when st_spi_read_bit =>

for i in 0 to miso'length - 1 loop -- miso'length is the number of SPI channels
memory(i) <= memory(i)(SPI_BITS - 2 downto 0) & miso(i);
end loop;

-- We used another counter here to record how many times shifted --

if (TO_INTEGER(UNSIGNED(cnt_spibits)) = SPI_BITS - 1) then

-- clear and go to next state

else

cnt_spibits <= cnt_spibits + 1;

end if;
----

At state st_spi_read_bit, miso bit will be shifted into memory. The SPI_BITS says 32, so it reads and shifts 32 times. We used another counter to record how many times the data are shifted, and confirmed it shifted 32 times in the read FPGA chip. But even it has 32 times, the result is still short a bit shift and data remains 1/2. The problem seems able to narrow down to this line, which requires to do 32 times in ModelSim, 33 times in real FGPA for correct data.

----
memory(i) <= memory(i)(SPI_BITS - 2 downto 0) & miso(i);
----

Does ModelSim has different interpretation of above line to Quartus?

Thanks for all opinions!