ModelSim simulation result is different to run in real FPGA
We use an EP1C6T144 chip as an SPI master to receive data from ADCs. The FPGA state machine is successful and receives data correctly in ModelSim simulation, but always shorts 1 bit shift if run on...
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Issue in setting up Nios 2 C/C++ Application on eclipse
hey, I installed the nios 2 software pack on my windows vista. When i try to create a project, it does not give me the option of "nios 2 c/c++ application on eclipse". Instead, i can create a simple...
View ArticleBug: Dynamic PLL phase shifting breaks clock compensation
We have just finished producing some prototype cards based on the Arria V GX (5AGXMA3D4F27C5) and have a problem with the fPLL behaviour. The setup is as follows: 1- An 125MHz input clock (N18+N19)...
View ArticleJTAG boundary scan fails on dut with ArriaII GX FPGA
Hi all, I already contacted JTAG Technologies support for this issue, but they advised me to get support from Altera... I have a PCB equipped with an NXP MCU and an ArriaII FPGA (EP2AGX95EF29). Both...
View ArticleGenerating mif files for PLL
Hello, Does anyone have an automated way (tcl) to generate mif files for PLL reconfiguration. I have about 2000 different frequencies I need to support and I'm not looking forward to doing it manually....
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logic primitives iobuf help
the quartus help not give the truth table for this part. give only little information . io.jpg list.jpg and were is OE pin ? . and how to active or disable output "i mean the output activated with high...
View ArticleData transfer
After having captured data from an ADC and stored it to the SDRAM on the DE0-Nano, what's the best way to transfer this data to the PC? I am currently just sending it over the JTAG UART using printf...
View ArticleActive serial programming not working Cyclone II starter development board
I am using Quartus II free web edition, 12.1 Build 177, not whatever was on CD that came in the starter kit, EP2C20F484C7N, (I used this version okay with CPLD EPM1270. The board has a EPCS4 on it, but...
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What is the suitable Voltage level for clock input? Vccio , Vccd_pll ?
I'm designing board with cyclone IV, so i was checking several reference designs, and I looked in the Cyclone III LS FPGA, in this design the designer set the bank 7 and bank 8 with a Vccio=1.8 (the...
View ArticleOpenCL License Issues
It would seem I may be having issues with my OpenCL License. All of the features in the license file show up as valid in Quartus EXCEPT openCL, but lmutil reports the OpenCL license as valid on the...
View ArticleEthernet IP Core
Hi, I would like to ask You the next question. The sending process to Avalon Bus controlled by ff_tx_sop and ff_tx_eop signals (in addition to other signals). In order to send user's data, Have I build...
View ArticleRTL simulation model of IS61LPS25636A
I'm trying to interface with the ssram of the cyclone iii starter kit. Does anyone know if there is an rtl model of the is61lps25636a ssram model available for download in order to perform simulations?...
View ArticleMulticycle custom instruction repeated calls, hangs, signals
Hello, I have some problems with a multicycle custom instruction. I'm using a Terasic DE1 board with Quartus II 13.01 64 bit on Ubuntu 12.04. I've started with the NIOS II system for "count_binary"...
View ArticleHow to export FIFO_OUT_CSR outside QSYS?
Hi, I have some Fifos inside Qsys system and I would like to export the FIFO_OUT_CSR to logic outside Qsys, using a Conduit Interface (PIO Parallel IO). However, the OUT_CSR is a Avalon Slave Interface...
View Articleconstant manipulation in VHDL statement
Hi, I am puzzled by the result of a VHDL code and hope someone could help understand the problem. ...... constant PERIOD : integer := 1000; constant A : integer := 4; constant B : integer := 23; .........
View ArticleConnect between Blocks at VHDL
Hi , i'm starting my final BS.c project and i'm doing it at Quartos and VHDL . I have blocks that i design at vhdl and i want to connect between them (logicly) , i know that there is an option to...
View ArticleZero Packed Or Unpacked Array Dimensions Problems
Hi bros. I want to implement a circuit that run like this: - If reset = 0, the output data = 12'b0; - If not, the output data = a vector in the ROM. And this is my code (I apologize for its length, but...
View ArticleStratix IV GT: Unknown PHY found at PHY address: Marvell 88E1111
I am currently working with the Stratix IV for 40Gbps development, and that is going well, but I am getting hung up on providing an interface for the main design via a simple socket server utilizing...
View ArticleOptimization Challenge
Hello, Pls do you know how i can stop the Quartus compiler from optimizing my code during synthesis? Am designing a ring oscillator and seems to me the compiler is optimizing the design to a single...
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