JTAG boundary scan fails on dut with ArriaII GX FPGA

Hi all,

I already contacted JTAG Technologies support for this issue, but they advised me to get support from Altera...

I have a PCB equipped with an NXP MCU and an ArriaII FPGA (EP2AGX95EF29). Both devices have their own boundary scan chain. I'm using a JT3705 from JTAG Technologies to perform the boundary scan tests. It downloaded the BSD file for the EP2AGX95EF29 from the Altera website (ftp://ftp.altera.com/outgoing/downlo...2AGX95EF29.bsd). The boundary scan tests fail on the EP2AGX95EF29:
- When executing the infrastructure test, the device ID returned by the FPGA is all zero's.
- When executing the ident test only, the correct device ID is returned. According to what I learned from the JTAG Technologies support, when the ident test is executed seperately, the IDCODE opcode is not used. The FPGA returns it's device ID by default, which seems to be a IEEE 1149.1 standard. When executing the entire infrastructure test, the device identity is checked by using the IDCODE opcode from the BSD file. Apparently, the FPGA is not interpreting this IDCODE opcode as it should be. Although the capture test is running well, which means the JTAG signals TDI, TDO, TCK and TMS are connected properly to the FPGA...
- When executing an interconnection test, all nets connected to the FPGA return errors, while nets only connected to the MCU are doing fine.

Since the BSD file is already over 2 years old, I doubt there is a severe error in this file. I suppose other people have used this file too. Could somebody point me in a direction where to search for what is going wrong here? All help is appreciated :-)

Best regards,
Wim