ModelSim vmake problem. Makefile is not properly formatted.
I'm running into an issue with generating a Makefile from ModelSim ASE 12.1 I start by running: $ vmake > Makefile And find that the resulting Makefile is not properly formatted. Instead of lines...
View ArticleError 10346: Formal port or parameter "write" must have a actual or default...
I use quartus II for VHDL compile work, and met this Error message: Error 10346: Formal port or parameter "write" must have a actual or default value As the "write" is the port of a SRAM, I don't know...
View Article$readmemb task trouble
Hi Guys, I have a problem with $readmemb :( This is my code: `timescale 1ns/100ps `include "rom_sin_vec.txt" module ROM_sin ( input clk, rst, input [10:0] addr, output reg [11:0] data ); reg [10:0]...
View ArticlePLL generation Error:"written by generation callback did not contain a module...
Hallo, today I tried to generate PLL through Qsys, but I am getting this error message: Quote: Error: altpll_0: File...
View ArticleAn all-in-one Software Defined Radio platform
Hi, I'm building the analog front end for my software defined radio receiver architecture. The ADC will directly sample the bandwidth of interest to basband where the the information can be passed into...
View ArticleMultiple kernels and logic utilisation.
Hi all, I am currently working on port a C library to OpenCL with the target platform being the Altera OpenCL (using the Bittware S5HQ PCIe). Essentially, I would like to have a library of kernels...
View ArticleDE0-Nano, Download .elf fail when using EPCS64
Hi, everyone~ I use DE0-Nano board, and I want to burn my .sof and .elf into flash memory, and make it self-booting. I use SDRAM as my memory in my SOC, and I have added EPCS Controller into it. Also I...
View ArticleQsys reset bus and its warnings
Hello guys, I am experiencing an interesting problem, where the Nios CPU, that has been working on Quartus 12.1 now resynthesized on Quartus 13.0sp1 doesn't work. I've also made a QSYS system...
View ArticleSoft ip core design
Hi, Basically i want to design one fifo soft ip core which should work any vendor FPGA.(I know so many fifo ip core's are there in market:-P). Already i designed fifo(256x8) using VHDL code and same i...
View ArticleCPLD vs FPGA:
So Lets say I wish to analyse pixel streams ( uncompressed DVI) I HAVE A 1 SECOND/16 000 000 time time window, until the next pixel. Multiple 24 bit parallel RGB combinations activate certain pins. I...
View ArticleGenerating a Motorola S-Record file for pre-programming CFI flash config PROM
Now that we have our product working nicely I need to generate a Motorola hex file (S-record) for a third party service to use to pre-program Spansion CFI flash PROMs that we use to configure a Cyclone...
View ArticleProblem to initialize M4K RAM from hex-file
Hi, I have created a Single-Port RAM definition (512 words, 9 bits wide) using the Quartus Megawizard, and use an Intel Hex file to initialize it, the problem is that the first address is always set to...
View ArticleHow about a verilog case statement that covers a range?
How about a verilog case statement that covers a range? e.g. : case(xcount) begin 1-100 : junk<=1; 101 : junk<=2; 102-200 : junk<=3; endcase
View Articleinterfacing of co2 sensor and zigbee with cyclone 4
i am doing project on fpga, my title of project is hardware reconfigurable wireless sensor node for real time application". i m using altera de2 115 which contains cyclone 4. i want to interface co2...
View ArticleDoes micron N25Q128 Quad SPI memory chip support AS configuration mode
Does micron N25Q128 Quad SPI memory chip support AS configuration mode for Cyclone V FPGA ?
View ArticleLicense file is not specified
I have been getting a License Setup Required dialog box when opening my Quartus Software. Each time I link to my valid license file and Quartus opens. Over a weeks period of time I may have to do this...
View ArticleHow to set avalon_tristate_slave to native address mode
HI,I know that when I create an avalon_slave (not tristate), I can choose addressing mode in deprecated setting. But there is no addressing mode in deprecated setting when I create an...
View ArticleHow should I write Verilog to describe DDR?
I have a design, which I need make the data is launched by double data rate (DDR). In this case, should I write the Verilog like this ? : always @(posedge clk or negedge clk) begin output <= a; end...
View Article"no rule to make target" error on nios software build tool
Hello everybody, I've got issues with Nios II SBT. I can't seem to have any sample project correctly built: All I really just do is choosing the template (in my case simple socket server) and the...
View Articleusing vga controller of de0 board in de0 nano board
Hi is it possible to use vga controller of de0 board provided in university programs in altera de0 nano board. If possible please guide me through it.
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