Quartus II Hangs with NFS
Dear Forum, I'm using Quartus II 13.0.1 build 232 64bit and OpenSUSE 12.3. If I place my projects on a disk accessed through NFS then Quartus hangs. The very same project placed on a local disk works...
View Articlehow to tell Quartus II which serial device (EPCS4) i am going to use to get...
Cyclone II eval board, i set target device as the fpga, when I open programmer (set to active serial programming) it seems to see board and shows EPCS4 device, but when I read my .pof file it says i...
View ArticleGolden Top Level Pin Mapping Error
Hello, I'm trying to compile the Golden_Top project provided in the examples of the SoC Development Kit. When compiling the fitter is generating the following errors: Code: Error (175019): Illegal...
View ArticleTriple Speed Ethernet: Do I have to edit *_tse_mac_constraints.sdc in a Qsys...
Hello, I'm working on a Qsys project where we use a Triple Speed Ethernet Core and I have troubles to correctly constrain my design. Also I'm a beginner when it comes to timing constraints. When I...
View ArticleWhen to use "set_clock_groups -exclusive"?
On my quest to learn timing constraints I stumbled on "set_clock_groups -exclusive" in the http://www.altera.com/support/exampl...3c120-qsys.zip example. According to the SDC and TimeQuest API Package...
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Triple speed ethernet performance
Hello, is somewhere some application note like was AN440, where they were tested some types of ethernet applications and table with benchmark test results (in attachment AN440) ? I use DP83848 with...
View Articlede0 nano control panel error
Hi i can able to write data to memory from control panel but while on reading to a file i cannot get the output i get an error load memory content to a file fail.. i get this error only when i try to...
View ArticleDDR3 SDRAM Controller with ALTMEMPHY for Stratix III in Quartus II V13.0
Doesn't MegaWizard Plug in Manager in Quartus II V13.0 support DDR3 SDRAM Controller with ALTMEMPHY for Stratix III? We have bought full version of Quartus II V13.0 and the Megawizard only seems to...
View ArticleHSMC-DVI adapter
I'm using a Terasic HSMC-DVI adapter(http://www.terasic.com.tw/cgi-bin/pa...o=359&PartNo=1) in conjunction with a Stratix IV FPGA(TR4 development kit). I'm wondering is anyone else has used the...
View Articlealtera_mult_add
Hey folks, I'm trying to using the new (Quartus 13.0, Stratix V) altera_mult_add IP. I just want to include the library at the top and drop the LPM component in without using the MegaWizard. In the...
View ArticleLocating PLLs, Transceivers, etc in Stratix V device with Chip Planner
How do I filter on the PLLs, Transceivers or any other block in the device view using Chip Planner? I'm targeting a Stratix V device 5SGXEA7N2F45C2. I've been able to use Find to locate the PLLs that...
View ArticleCode size / Due to STL?
Hello, I recently started with the NIOS II. I started from the 'small C hello world' example and simply added C++ support. Now, when I want to use a vector<int> for instance, the code instantly...
View ArticleControlling HPS EMAC from FPGA Fabric (Nios II)
I would like to know if the Ethernet port (EMAC0) can be controlled by the NIOS in the FPGA Fabric. From the documentation it seems possible but it is not 100% clear that this HPS peripheral can be...
View ArticleIs there a program to convert AHDL to VHDL?
I have an ancient EP1K design mostly in AHDL with one VHDL sub-module. Is there any way to automatically convert it to VHDL?
View ArticlePrograming the EPCS4 with SOF & ELF Files
Hi... I had tried to program the .jic file with a lot of different methods given on the Altera forum. The device is successfully programed but the Nios processor doesnt boot from the epcs. Means the...
View ArticleAdd test bench to project at modelsim
Hi , i create new project at modelsim and wrote hdl design and there aren't errors . i create test bench file at VHDL and i need to add the file to the project and compile the test bench , How do i do...
View ArticleComparator challenge (FPGA)
Hello frndz, Again, i want to design a comparator that can compare two analog voltage (e.g 3.0v and 1.5v) for a STRATIX III FPGA. Meaning my design is supposed to be digital using VHDL. The comparator...
View ArticleSPI Slave firmware upgrade
Hello folks !! I'm writing because I need some suggestions on how to upgrade the firmware on a SPI slave. In this scenario I have a .txt file which contains the bytes I need to send, via SPI protocol,...
View ArticleDDR3 UniPHY problems
Hello, I am trying to incude a DDR3 UniPHY Controller megacore to my design, but I am experiencing several issues. I am working on a TR4 development kit (TERASIC) based on the STRATIX IV FPGA...
View ArticleForming a tightly coupled memory system in Qsys
Hey, I am trying to generate a custom component which is tightly coupled with the onchip memory. The problem is that the qsys exposes only the port of the onchip memory rather than the individual...
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