Hi ,
i create new project at modelsim and wrote hdl design and there aren't errors .
i create test bench file at VHDL and i need to add the file to the project and compile the test bench ,
How do i do it ?
thanks .
i create new project at modelsim and wrote hdl design and there aren't errors .
i create test bench file at VHDL and i need to add the file to the project and compile the test bench ,
How do i do it ?
thanks .