Soft ip core design

Hi,
Basically i want to design one fifo soft ip core which should work any vendor FPGA.(I know so many fifo ip core's are there in market:-P). Already i designed fifo(256x8) using VHDL code and same i tested in one of my project and its working nicely.I just want to know how to make one reliable ip core from RTL code which should work any vendor FPGA(using one common netlist)? i am zero in IP CORE design.Can anyone tell me how to learn basic things about SOFT IP CORE DESIGN?

Thanks and Regards
Karthi.S