DE2 Laboratory 8 bit wide mux (VHDL)

Hi guys,
After 10 years of leaving high school, and 5 years after purchasing a DE2 board, I found time again to start playing with FPGA’s.
So I started where everybody does (I think), with the lab exercises. And I’m already struggling with the 2^nd part of the 1^st lab.
The exercise is to make an 8 bit wide, 2-to-1 mux.
My code is:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY entitypart2 IS
PORT( x : IN std_logic_vector (7 DOWNTO 0);
y : IN std_logic_vector (7 DOWNTO 0);
s : IN std_logic;
M : OUT std_logic_vector (7 DOWNTO 0);
ledupper : OUT std_logic_vector (7 DOWNTO 0);
ledlower : OUT std_logic_vector (7 DOWNTO 0));
END entitypart2;

ARCHITECTURE mux OF entitypart2 IS
BEGIN
ledupper <= y;
ledlower <= x;
M <= x WHEN (s = '0') ELSE y;
END mux;

X and y are routed to switches 0 to 7 and 8 to 15, M is routed to the green LED’s. The “ledupper” and “ledlower” are just added to see if something happens when I switch.

The problem is: nothing happens!! If you don´t count that only LEDG7 goes on when I switch SW4 and all the red LED’s are on.
What is wrong? In the RTL viewer, I see a (one) nice 2-to1 mux with x and y as input bus and M as output bus.
Do I have to see 8 different mux’es?