DE2 Laboratory 8 bit wide mux (VHDL)
Hi guys, After 10 years of leaving high school, and 5 years after purchasing a DE2 board, I found time again to start playing with FPGAÂ’s. So I started where everybody does (I think), with the lab...
View ArticleError (10481):Keccack hash functions
Hello guys i a trying to implement a keccak hash algorithm.I got the following error message Error (10481): VHDL Use Clause error at keccak.vhd(213): design library "ieee" does not contain primary unit...
View ArticleClik here to view.
Much of two months wasted through compiler changes - Quartus v13.0 sp1.
Back in 2008 I designed and built a Cyclone I based USB interfaced instrument, which has been working flawlessly in my academic research lab 24/7. However that FPGA module is no longer available, and...
View ArticleAre there any appearance differences in EP3C40F780C8N with respect to PCN1205?
I read the notification document and it states this part will transition to center pin gate mold after date code 1249. But my device with date code 1325 shows no difference with those products before...
View ArticleClik here to view.
SGDMA behaves badly if its descriptors are in off-chip RAM?
I observed some odd SGDMA behavior today. Does SGDMA behave badly if its descriptors are in off-chip RAM? In any case I think I see it copying the wrong data in the attached signal tap output. The...
View ArticleI2C Level Shift use PLD
Does anyone know how to implement a i2c level shift use PLD, verilog or vhdl is OK. Thanks advance!
View ArticleProgramming hardware cable not detected
Hi, I'm using Nallatech PCIE-385n a7 version. I've driver and SDK installed without problems, but when I try to flash it I got the following message: aocl flash: Running flash from...
View Articlehow can I use HSP GPIO interrupt
I just want a simple example about how to use the gpio interrupt. My problem is that I can't get the gpio interrupt map in http://www.altera.com/literature/hb/...v/cv_54006.pdf page6-12. Does the gpio...
View Articlewhy the waitrequest signal is always 0
hi,all.I wanna use an arbitrator for two frame buffer to access the DDR3 SDRAM (IP:DDR3 SDRAM Controller with UniPHY Device:cyclone V Tool:QuartusII 13.0).But I find the read_waitrequest and...
View ArticleAOCL Report Output
I am trying to offload computations from CPU to FPGA. When I compile my opencl kernel with the report option enabled I get the following output: aoc: Selected target board pcie385n_a7 Kernel throughput...
View ArticleSimulation of PCI-E Harc IP in Modelsim Altera Starter
Hi, I'm trying to simulate PCI-Express example designs which are added to Quartus 11.1, but in every case Modelsim shows some files not found ie. Instantiation of 'arriav_hd_altpe2_hip_top_encrypted'...
View Articlewhich FPGA series support HDMI 2.0?
Hi, I am using Altera Startix 4 GX, i am interested in HDMI output. In the specification they didn't precise whish HDMI is supported 1.3 or 1.4a or.. I have two question: How I can knox the hdmi...
View Articlenios ii sbt for eclipse | nios ii bsp editor | Drivers tab | missing check box
Hi, We want to enable the driver with module name = LCD_subsystem_sgdma. In the Drivers tab, the entry for the module has no check box. What do we have to do to make a check box appear so we can check...
View Articlebest FPGA board for display via hdmi 2.0
Hello, I'm new in the forum .. also a "litle beginner" .. this is my first post so admins. are welcome to move this thread to another forum if appropiated. What do you think guys is the best fpga board...
View ArticleClik here to view.
Clocked Video Output :Standalone CVO block for controlling DVI monitor
I'm developing an imaging system using the TR4 development kit. Specifically, I'm feeding raw digital data into the FPGA and driving this raw data into a DVI connector(by way of the Bitech HSMC-DVI...
View ArticleTSE Gigabit will not generate TX pause frames
Hello, I have done everything I can see to try for over a day now but have been unable to get pause frames to be transmitted on a Gigabit link. Even with XOFF_GEN set in the command register none are...
View ArticleVery basic SignalTap question
Hello, I have inherited an old Cyclone II design which is mainly implemented in schematic. I am staying with the older version of Quartus for now (9.1) since there's a lot of native simulation files....
View ArticleNeed help with my .vwf file to simulate my vhdl design file
I'm having an awful time getting my vwf file to simulate correctly. I just keep running into errors. Can someone help me out or point me in the right direction on how to set this up. I understand there...
View Article[Cyclone III DEV KIT DK-DEV-3C120N] Flash Erase fails at 0x02900000
Does anyone have any idea why I can not erase the flash completely? I tried using Quartus II Programmer as well as with nios2 command shell. I tried different versions from 11.1 to 13.0. Erase in...
View Articledata rate of EP4CE40F29C7N
I just working around with a design of wireless device with EP4CE40F29C7N. But what is the aggregate single peak data rate of this ? I can only find the data rate info about the GX device, but seems...
View Article