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Syntax error, unexpected integer number, expecting identifier
Hello there. I am starter at FPGA. I've advanced digital design course at my M.Sc class. Lecturer give us a homework about on Quartus 2,creating schematic designs, graphical test vector and simulate...
View Articlealtera Startix GX 530
Hi to all, does any body know which hdmi version have the startix 530 GX ?(1.3 or 1.4) does anybody know an FPGA board how implement the hdmi 1.4 with interlaken as input and hdmi 1.4 as output? Thx in...
View ArticleQuartus II web edition
Hi , i am a Electrical Engennering student at Afeka college at Tel Aviv,Israel. I download "Quartus II Web Edition Software Version 12.1 Service Pack 1 for Windows " from the Altera official website...
View Articlethe qxp file show detailed hierarchy information, could it be hidden?
I want to deliver the qxp file to customer. But the detailed hierarchy information of qxp was shown by quartus tool. I don't want to show the hierarchy information to customer, could it be hidden?
View ArticleUART and XBee and NIOS II
Hello, I need help. Based on my intensive internet search, all I need to connect to an Zigbee network using the FPGA (NIOS II) is a UART. Here are my queries: (1) Can I use...
View ArticleConnected system ID hash not found on target at expected base address.
Hi, I do get the following error message when I want to download the elf file with the NIOS II Eclipse tooling: Unable to validate connection settings. Connected system ID hash not found on target at...
View ArticleClock pins for Stratix IV E FPGA
Hello, I am supposedly failing to figure out the correct clock pins for the Stratix IV FPGA. I want to drive a PLL with a 100MHz clock but from what I get from the reference manual, the clocks aren't...
View ArticleLoad custom-data to On-Chip memory
Folks, what would be the best way to load custom data to the on-chip memory of a Cyclone IV FPGA, preferably at start up. Eventually a NIOS II application reads data from a flash device and stores it...
View ArticleSerial connection for DE2 is not working
When I look in the manual it says that serial connection should work but when I try to run the program it is not working and not even code formatting in the Nios 2 IDE works. Code: /* A simple program...
View ArticleSource synchronous input clock and no output clock constraints
For my Stratix V design, a source synchronous, 4ns period, input clock is used to clock input data. The output data is clocked out of the FPGA back to the source clock without a TX clock. The external...
View ArticleModelBus - RegField
Good afternoon, I have a nice DSP Builder model integrated with a NIOS II processor. Everything works well. I'm trying to use the RegField in the DSP Builder Advanced Blocks/ModelBus library. After...
View ArticleHow to implement very basic custom QSys component
I know this question has to have been posted and answered, but I can't find it in a way I can understand and solve my problem. My effort is very basic and I'm new to the QSys way of FPGAs. Basically,...
View ArticleDesigning without Quartus II
Is there a way to specify a design entirely by hand without Quartus? I am asking because my research project on asynchronous circuits requires full control of wiring and logic gate placement....
View ArticleCreate custom precompiled library
Hello people, I have a small to medium experience with Quartus II but I haven't figured that out yet. I want to create a small collection of VHDL entities that I use a lot (for example a PWM block, an...
View ArticleIs it possible to program Flex series chips with Quartus II?
Hi, I had Max+Plus II software which I was using to program my legacy Flex 6000 series chips. But my computer recently died. I also have a Quartus paid version on another computer. IS there a way to...
View Articleclock cycles consumed by NIOSII C code
Hello, I have a design implemented in NIOS processor. I am using DE1 board. I want to calculate the performance/clock cycles consumed by my C code from some specified instruction to some specified...
View ArticleDisable DSB block input and output register moving
Hi, I have an issue with DSP blocks that they are inferred by the synthesiser but the input and output registers are placed into logic. After that during Place & Route it's decided by the tool...
View ArticleLink to SRAM Qsys Tutorial 8 Bit sought
Hmm like many others I'm stunned at how difficult it is to add an SRAM component to a NIOS system. Two days and so far all I can get is a mishmash of signals that seem to bear no relation to the pins I...
View ArticleHow to get the Control Design In Quartus
Hello All I am trying to design th 32 bit ALU with 5 function as given in this slide presentation http://www.cse.ohio-state.edu/~crawf..._ALUDesign.pdf While Designing 1 Bit ALU I am stuck how to...
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