Source synchronous input clock and no output clock constraints

For my Stratix V design, a source synchronous, 4ns period, input clock is used to clock input data. The output data is clocked out of the FPGA back to the source clock without a TX clock. The external device's clock is used. Below are my timing constraints.

create_clock -name rx_phy_pipe_clk -period 4 [get_ports {rx_phy_pipe_clk}]

derive_pll_clocks

derive_clock_uncertainty

#virtual clock - source clock
create_clock -name rx_phy_pipe_clk_ext -period 4.0

set_input_delay -clock { rx_phy_pipe_clk_ext } -max 0.8 [get_ports {phy_mac_*}]
set_input_delay -clock { rx_phy_pipe_clk_ext } -max -0.8 [get_ports {phy_mac_*}]

set_output_delay -clock { rx_phy_pipe_clk_ext } -max 1.7 [get_ports {mac_phy_*}]
set_output_delay -clock { rx_phy_pipe_clk_ext } -min -0.1 [get_ports {mac_phy_*}]

From TimingQuest, I get setup violations to rx_phy_pipe_clk_ext. The data arrival path is 5.809ns (3.008 clock and 2.801 data) and data required path is 2.240ns. I believe I need to add a negative phase shift to reduce the clock delay on the data path. I've tried this but then I get failures elsewhere. Do I need to add multi-cycle path constraint on both inputs and outputs?

Any help is much appreciated!