Cannot load PCIe driver into the linux of Atom, De2i-150
I followed everything that the manual said to build a PCIe system using Qsys, where user logic has nothing else but a LED I/O. I generated the Qsys and loaded the *.sof file onto the board, and...
View Article7 Segment decoder help
Hi, I am new to VHDL and trying to create a VHDL module for a 7 segment decoder. The code I used is below Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use...
View ArticleSPI slave code
Hi, I'm using the QSYS SPI module as a slave. The SPI slave is supposed to receive sequences of bytes/characters. In order to make this happen, I'm using some SW code that reads the status register and...
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Triple speed ethernet IP core don't receive the RGMII data?
I use the triple speed ethernet IP core with an external PHY Device, the first picture is shown as my test block diagram . Transmiting part works normally, however, There is no data on the avalon-ST...
View ArticleNativeLink error in Quartus II 13.1 for Modelsim
Hello people, I am having a completely ununderstandable error. After I compile my code in Quartus II 13.1 and try to run Modelsim through Quartus (Nativelink) I get a strange error: NONE. Check the...
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problem with Nios II Eclipse
Hi, I am trying to run an application c program with Nios II Eclipse for triple speed Ethernet(TSE_MAC) and getting following error: in attachment (screenshot). 1.JPG what could be the reason? Attached...
View ArticleDefault port values missing error during compilation
I have a small .bdf file and another VHDL file instantiated inside this .bdf. I created this bdf just to test the small VHDL file I am creating. The thing is that I test it step by step and I have an...
View ArticleCyclone V LVDS differential termination and RZQ
Hello, I am designing a board with differential LVDS interfaces (receive). I want to use the internal differential termination Rd and the manual is not very explicit on whether the RZQ resistor has to...
View ArticleRead Write to DRAM (main memory)
I am just switching from another fpga to altera. Could you please tell me is this the write way to access main memory. main_memory = (char *) DDR2_SDRAM_BASEADDR; // base address of main memory can be...
View ArticleA FIR FILTER , I cant understand
hi everyone: I just read a part of vhdl code . The code is used to do filtering. The data avSigCreg(9) which is summed will be taken into a digital filter. The code is shown below: -------------------...
View ArticleQuartus 13.0 - Linux version - virtualized by Parallels
Hi everybody, I would change my PC with a macbook pro. I use quartus II v.13.0 on Linux Ubuntu 12.04, and It works very well. In particular my project is based on DE4 board, so I always change the arp...
View ArticleSD Card Fat16 not recognized - up sdcard interface
Hi, when I try to start the university test program in Eclipse, it says that the sdcard is inserted but the File System is unkown. I tried with different sdcards but the problem remains. I tried to...
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Migration of Qsys PCIe IP Core from 13.0SP1 to 13.1 failed
Hello all, It seems that migration of my PCIe IP from 13.0SP1 to 13.1 failed. Specifically, I'm getting this error: Code: Info (12128): Elaborating entity "altpciexpav_stif_a2p_vartrans" for hierarchy...
View ArticleHow to organize data stream through AMBA bus between FPGA and HPS (with Linux)?
Hi everybody, I'm currently looking into how to transfer data between HPS and FPGA via AMBA AXI-interface. HPS is supposed to run Linux. Is it possible to do it using board support package provided by...
View ArticleUse a high speed transceiver to transmit an arbitrary clock?
Hello, Is there a way to use a high speed transceiver on a Stratix V to transmit an arbitrary clock? I would like to create a synchronous high speed serial link between two boards, but operating at a...
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Train ticket machine vhdl code
Hello. I am new in VHDL. I try to create train ticket machine using vhdl. It have 3 destination and all destination have fee. When user insert money with same of fee, ticket will out and no change but...
View ArticleHow to initialize SD-Card with SPI Command?
Hi, I implemented the Altera SPI Core in my SoPC. Altera provides one access routine "alt_avalon_spi_command()". How exactly can I implement the typical SD-Card Initialization in my Code? Altera SPI...
View ArticleUsing 7 segment on De1 Board
Hello to every one, I've just bought the DE1 board and i try to do some sample program with VHDL like put led on when switch is on and something similar. I kindly ask you if you can tell me how i can...
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Strange simulation results
Hi, I've been playing around with my models behavior to try and combine it into one process. However when I simulate it I am getting some odd results. Iv'e attached a jpeg of the testbench results. 1....
View ArticleFor loop, array and a step motor, VHDL
I'm trying to implement a sequence in order to use a step motor using VHDL. Since I'm really new to VHDL I can't see what's missing in my code. I want to loop through an array to give the different...
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