I'm trying to implement a sequence in order to use a step motor using VHDL. Since I'm really new to VHDL I can't see what's missing in my code. I want to loop through an array to give the different steps to my variable named motor.
I'd appreciate any help.
These are the errors:
I'd appreciate any help.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity main is
Port ( motor : out STD_LOGIC_VECTOR (3 downto 0));
end main;
architecture Behavioral of main is
type my_array is array (0 to 6) of std_logic_vector(2 downto 0);
signal secuencia : my_array;
secuencia := ("0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111");
begin
variable i : std_logic:= '1';
for i in secuencia' range loop
motor <= secuencia(i);
end loop;
end Behavioral;These are the errors:
Code:
ERROR:HDLCompiler:806 - "C:/Users/main.vhd" Line 12: Syntax error near "secuencia".
ERROR:HDLCompiler:806 - "C:/Users/main.vhd" Line 15: Syntax error near ":=".
ERROR:HDLCompiler:806 - "C:/Users/main.vhd" Line 16: Syntax error near "loop".
ERROR:HDLCompiler:806 - "C:/Users/main.vhd" Line 18: Syntax error near "loop".
ERROR:ProjectMgmt:496 - 4 error(s) found while parsing design hierarchy.