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DDR2 SDRAM controller for mt47h64m16hr-3
Hello. I am trying to implement a DDR SDRAM controller with ALTMEMPHY for MICRON mt47h64m16hr-3 according to a tutorial on http://www.hdl.co.jp/en/index.php/ac...c20130115.html. However, a problem is...
View ArticleHow get I get rid of installed driver
I've been playing around (to learn) with sw.tcl for my interface. It isn't quite right and I need to progress beyond that for now and will come back to it later. It's actual a sw package, or bsp lib,...
View ArticleUsing Fpga to HPS bridge
I have an ADC board connected to SOC kit and the FPGA recieves ADC samples at 10Mhz rate. I would like to transfer those samples to HPS and do some processing and send those processed samples back to...
View ArticleIP Security with DS28E01 and Cyclone 4E - Altera Reference Design Integration...
Hello, i try to integrate the Reference Design into my Design. I use the Dual-Purpose Pin "Flash_nCE/nCSO as regular I/O after configuration" for the One Wire Interface. Externally i have an Pullup...
View ArticleUsing tristate bridge with de0 nano (cyclone IVe
Hello, I try since a couple of days to get cs, read and write signal on outputs of my de0 nano board. The goal is to drive a motor controller (LM628) which needs ck 8Mhz, cd, rd ,wr and a 8 bits data...
View ArticleRecord execution time in nios ii
Hi, I have a custom component in my qsys project and I want to record the processing time in the component by using 'clock()' in the nios C code. The problem is whenever I add these lines:...
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on chip FIFO memory question
Hello, I met a question when add on-chip FIFO memory in Qsys. when writing data to FIFO core, it can result in PC hung up. pls see the attached file for details would you please help me? Thanks...
View Articlevery simple PLL usage issue
Hello, I'm working on a custom pcb with a cyclone V GX. I'm having issues getting an output from the altera megafunction PLL, it is unresponsive. My test design has a nios II which successfully runs...
View ArticleQuartus TCL Problems - get_all_global_assignments
I'm trying to figure out how to use the get_all_global_assignments TCL command. I might be using it incorrectly, but I strongly suspect there is a bug in the tool. I have a project who's qsf file is as...
View ArticleHow to solve NIOS and C++ problem with alt_remap_uncached
I'm using NIOSII eds for an app in my SOC. I'd like to use C++, but I'm having problems even getting it started. What am I missing here? extern "C" { #include <stdio.h> #include "system.h"...
View ArticleGUI touchscreen tool
Hello all, I'm looking for a good tool that allow me to design GUI touchscreen display (menu, buttons). A very easy and fast for my development work. Does anybody know the tools to do that? Best, Sean
View ArticlePacking DSP blocks
On 3-12 of Stratix V manual it states each DSP block can support 3 independent, 9x9 multipliers. When I synthesize it puts them in 3 separate DSP blocks. How do I get it to pack it into 1 DSP block? I...
View ArticleTimeQuest Timing issue
Hi, After my full compilation to my design, TimeQuest Timing Analyzer gives out lot of red lines. Under the folder of " Slow 1100mV 85C Model" the Fmax Summary displays the Fmax=111.72MHz and...
View Articleproblem of online training
in a day there is always a period in the morning, i can not loggin in the online training page, when click on the url, it shows Error 404--Not Found is the website still in an updating process?
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Running Quartus 13.0sp1 Triple Speed Ethernet IP on uClinux
Hi, I have had no luck getting the Ethernet connection working and am hoping someone could provide some guidance. I have a Cyclone V GX development board running uClinux but I would like to enhance it,...
View ArticleDC-DC step down in FPGA
Hello there, I have DC volt in 200V, out 50V, and I out 60A soft switch. I wonder any TI chips filter can handle this kinds of voltage. I want to use FPGA to control digital. multi phase power. Thanks,
View ArticleXCVR TK STRATIX V issue
Hello I am using the transceiver toolkit (XCVR TK) for analyzing a transciever channel between ARRIA V and STRATIX V FPGA's . The data rate is within both FPGA's range (~2Gbps). When I use the basic...
View ArticleClock Pins in Cyclone V
Hello, If I want to connect HSMA_CLK_IN_P2/N2 (which refers to CLK7p/n on my 5CSXFC6D6F31C8NES) to a PLL, I have to place the PLL in one of the two quadrants on the right of the chip, am I right? By...
View ArticleIs there a way to reducethe ressource usage of QSYS interconnects?
Hi, as time passed, my design grew and grew. In the meantime its ressource usage on my 4C75 is 85% or 63.600 LEs. I noticed that 58.000 LEs are needed by my QSYS-System and within this 3.400 LEs are...
View Articlehow to load a image in quartus II tool and convert it into a .dat file
i am doing final year project on image processing and i have to convert a image file into .dat file in quartus II tool so that i can use it as a input to my architecture and project is on image...
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