Quantcast
Channel: Altera Forums
Viewing all articles
Browse latest Browse all 19390

Is there a way to reducethe ressource usage of QSYS interconnects?

$
0
0
Hi,

as time passed, my design grew and grew. In the meantime its ressource usage on my 4C75 is 85% or 63.600 LEs.
I noticed that 58.000 LEs are needed by my QSYS-System and within this 3.400 LEs are needed by "QSYS_mm_interconnect_0" and 47.800 LEs are needed by "QSYS_mm_interconnect_1".

That means about 80% of the design ressources are needed only for the QSYS interconnects.

I think I'm doing something terribly wrong.......

My QSYS-System consists of a PCIe-HIP as MM-Master with two BARs:
BAR2 contains the mSGDMA-Core and the Read- and Write-Masters to some FiFos.
BAR0 contains everything else like a bunch of PIOs (about 40 to 50), Tristate Conduit and other Memory-Controllers.

I don't want to speed up BAR0, because there are no timing critical devices on it. But I wonder if there is a way to reduce the Ressource-Usage.

I tried to use this: http://www.altera.com/literature/hb/...s_optimize.pdf but the examples for reducing Logic have multiple Masters. I only have one Master per BAR.

Does anyone know some help?

Viewing all articles
Browse latest Browse all 19390


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>