Hello all,
It seems that migration of my PCIe IP from 13.0SP1 to 13.1 failed. Specifically, I'm getting this error:
And I'm curious why this happens. I'm by no means an expert on PCIe or Verilog.
I have included the file.
It seems that migration of my PCIe IP from 13.0SP1 to 13.1 failed. Specifically, I'm getting this error:
Code:
Info (12128): Elaborating entity "altpciexpav_stif_a2p_vartrans" for hierarchy "de2i150_core:u0|de2i150_core_pcie_hard_ip_0:pcie_hard_ip_0|altpcie_hip_pipen1b_qsys:pcie_internal_hip|altpciexpav_stif_app:avalon_stream_hip_qsys.avalon_bridge|altpciexpav_stif_tx:tx|altpciexpav_stif_a2p_addrtrans:a2p_addr_trans|altpciexpav_stif_a2p_vartrans:vartrans"Error (10198): Verilog HDL error at altpciexpav_stif_a2p_vartrans.v(121): part-select direction is opposite from prefix index direction
Error (10784): HDL error at altpciexpav_stif_a2p_vartrans.v(52): see declaration for object "PbaAddress_i"
Error (12152): Can't elaborate user hierarchy "de2i150_core:u0|de2i150_core_pcie_hard_ip_0:pcie_hard_ip_0|altpcie_hip_pipen1b_qsys:pcie_internal_hip|altpciexpav_stif_app:avalon_stream_hip_qsys.avalon_bridge|altpciexpav_stif_tx:tx|altpciexpav_stif_a2p_addrtrans:a2p_addr_trans|altpciexpav_stif_a2p_vartrans:vartrans"
Info (144001): Generated suppressed messages file ...
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 124 warnings
Error: Peak virtual memory: 789 megabytes
Error: Processing ended: Sat Nov 16 15:48:15 2013
Error: Elapsed time: 00:00:31
Error: Total CPU time (on all processors): 00:00:42
Error (293001): Quartus II Full Compilation was unsuccessful. 5 errors, 124 warningsI have included the file.